**** **** ****** ********* #**, San Diego, CA 92115
Phone: +1-619-***-**** Email: email@example.com LinkedIn: www.linkedin.com/in/harshilk93 EDUCATION
Master in Electrical and Computer Engineering Expected – Aug, 2017 San Diego State University, CA (GPA 3.4/4.0)
Bachelor in Electrical & Electronics Engineering May, 2014 Gujarat Technological University, India (GPA 8.77/10) RELEVENT COURSE WORK
VLSI System Design, VLSI Circuit Design, VLSI ASICs Design, RTL Design, CMOS Logic Design, Digital Logic Design, Computer Architecture, Signal and Power Integrity, Digital Signal Processing, Modem Design. WORK EXPERIENCE
Technical Product Specialist – Optifuse, El Cajon, CA Feb 2017 – May 2017
Working with the electrical engineering team for developing the Micro, Surface Mount fuses for PCB and Automobile applications. Development of Technical specification sheets for the Micro-electronic part which we designed.
Instructional Student Assistant – ECE Dept., SDSU Jan 2016 – Dec 2016
Teaching assistant and Grader for courses Microprocessor and Digital Systems.
Instructing and helping students understand the course material, class assignments and projects.
Assistant Electrical Engineer - Subham Industries, India Nov 2012 – Jul 2015
Collaborated with four team members to design custom based industrial automation products and testing.
Worked on the technology named Numerical Control Frequency Conversion (NCFC) for the fast production by having various speed, frequency and phase depends on application for the manufacturing & testing department. RESEARCH EXPERIENCE
Graduate Research Assistant – VLSI Design and Testing Lab, SDSU Jan 2016 – Present
Working on Hardware and FPGA implementation of “An Efficient Hardware Implementation of Filter for Signals with Large Ratio of Sample Rate to Bandwidth” for improved chip area and power consumption, includes PLL design.
Worked on Hardware implementation of “Stable Design and Efficient Hardware Realization of Narrow Bandwidth Low- Pass Poly-phase Recursive Filters” for high throughput and stable realization using first and second all-pass filter structures.
Tools used: MATLAB, Xilinx Vivado, ISE Design Suit, Synopsys Design Compiler. TECHNICAL SKILLS
Programming Skills : Verilog, System Verilog, Python, C, C++, MATLAB ASIC Design Tools : Synopsys Design Vision & IC Counter, Cadence Encounter Virtuoso, Mentor Graphics ICstation FPGA Design Tools : Xilinx Vivado, ISE Design Suit Simulation Tools : Key-sight ADS, Maxwell 2D, PSpice, Cadence Virtuoso Schematic and Layout Editor, NC-Verilog, Synopsys Primetime (Static Timing Analysis)
Bus Protocol : AXI, SPI, UART, I2C
FPGA and ASIC implementation of high Speed Parallel Bubble Sort using Xilinx Vivado, Cadence Encounter and Synopsys Design Compiler, implemented on Spartan – 6 FPGA board.
High speed differential transmission line model design by using Roger tool, Key-sight ADS and Maxwell 2D simulator. Design was being created and simulated at data rate 10Gbps in ADS to observe the eye pattern and S-parameters.
Designed parametric hardware for UART protocol with 9600, 19200, 38400 and 57600 baud rates. Implemented serial communication between computer and Artix-7 FPGA board.
Simulated a QPSK modem using a complex baseband modulator with SQRT Nyquist shaping filter using MATLAB. Implemented frequency lock loop, timing recovery and phase lock loop with 20 tap equalizer using LMS algorithm.
Implemented hardware for parametric tap FIR and IIR filters with Time Multiplexed and Pipelined architectures. Achieved 180 MHz throughput on Artix-7 FPGA board using fixed point adder and multiplier modules.
8th order IIR Filter using 4 Second Order Sections with parameterize data-path bit-widths using time-multiplexed computational units on FPGA using Xilinx ISE and MATLAB.
H. Shah, D. Karyodisa, A. Alimohammad and f. harris, “Stable Design and Efficient Hardware Implementation of Narrow Bandwidth Low-Pass Polyphase Recursive Filters”, submitted to IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, February 2017. EXTRA-CURRICULAR ACTIVITIES
Participated in conference of Center for Sensorimotor Neural Engineering (CSNE), University of Washington, Seattle. Developed the hardware for parametric artificial neural network which can adopt the weights and classify the inputs using Verilog.