Design Control

RESUME of:

Andrew P. Kisylia

A.P.K. Engineering, Inc.

***** ******* **

Camarillo. California 93012

Cell: 818-***-****:

E-mail: *********@*****.***

Web Site: www.apkengineeringinc.com

SUMMARY OF QUALIFICATIONS:

Owner and principle engineer of APK Engineering, Inc., an “Electronic Design Consultancy” since 1980.

I have a demonstrated track record in responding to the continually changing technology, customer requirements and expectations.

Expertise in hardware design (analog and digital), software design and hardware implementation (printed circuit board capture and layout)

I have been, and continue to be, a major participant in numerous “state of the art” engineering projects.

My experience covers both the military and commercial environments.

I have held a Security Clearance in the past, but not currently.

My references are available or request.

FORMAL EDUCATION/TRAINING

BSEE from the University of Notre Dame, Notre Dame, Indiana.

MSEE from the University of Illinois, Champagne/Urbana, Illinois.

Post Masters Studies Toward a PhD in Computer Science at UCLA

Numerous vendor presented workshops and seminars related to both hardware and software techniques.

PROFESSIONAL SOCIETIES, PATENTS & PUBLICATIONS

ETA KAPA NU

TAU BETA PI

I.E.E.E.

Patent No. US05778074, Methods for generating variable S-boxes from arbitrary keys of arbitrary length including methods, which allow rapid key changes.

Patent No. US05583398, Power factor correcting fly back arrangement having a resonant capacitor element connected across the switching element.

Patent No. US03988717, General-purpose computer or logic chip and system.

Masters Thesis: “An Association Processor for Information Retrieval”, Coordinated Science Laboratory, University of Illinois, Urbana, Illinois.

EXPERIENCE:

7/20/13 to Present Karem Aircraft, Inc. Lake Forest, CA

Designing aircraft quality FPGA/Microcontroller based interface equipment. The tasks include Electronic and Logical design, Schematic Capture (Cadence OrCAD) Printed Circuit Board design and layout, FPGA Code design, Board assembly, FPGA test code (Verilog) and Unit test

Currently designing, fabricating and testing a “Smart Small Servo Module” (SSSM) for the control of the Kollmorgan KBM(S) series of brushless DC servo motors. Direct motor control is via a Fairchild “Smart Power Module”. These motors are used to position of the flight control surfaces of Aircraft wings.

The SSSM contains an FPGA embedded multi-channel Ethernet interface, a microprocessor controlled 600V-10A 3-phase IGBT inverter bridge motor drive and complement of sensors for real-time control of motor rotation and position.

>The control microprocessor is an STM32F407 with integrated interfaces

>The development system used is: IAR Embedded Workbench

>The software was written in C, C++.

>The FPGA Programmed is a 75K gate Xilinx Spartan 6.

>The development system used is: Xilinx ISE Design Suite 1.3

>The FPGA program was developed and executed in Verilog

>FPGA Simulations were executed in Modelsim.

>The Fairchild “Smart Power Module” is an FSBB0CH60C.

> Developed FPGA test code (Verilog) for Unit test

6/2013 to 1/2014 Irvine Sensors. Costa Mesa, CA

Participated during the testing phase of the development of a new MEMS gyro. This gyro is based on high frequency techniques on the order of 4 GHZ. I provided consultation expertise in the areas of Verilog code modification and C++ software corrections in both the hardware and software control of the real time control processes.

I was also directly responsible for the test of the first two full-speed prototype Assemblies. The testing included the modification and the verification of both the hardware and the controlling firmware and software.

4/2012 to 9/2012 EON Instrumentation, Inc. Van Nuys, CA

Designed FPGA program for new Radar Blanking Unit under contract for the Navy. The Blanking Unit is programmable with 93 unique pre-settable Delay and Blanking intervals timed from 31 radar synch inputs. These 93 blanking signals can be combined into 8 unique radar blanking controls.

>The FPGA Programmed is a 100K gate Xilinx Spartan 6.

>The program and simulations were executed in Verilog

12/2011 to 2/2012 ImThera Medical Inc. San Diego, CA

Conducted a Critical Design Review of an implantable Neuro-Stimulator ASIC to alleviate sleep apnea. This custom ASIC consisted of both digital and analog technologies.

6/2011 to 10/2011 JFA Systems, Inc. Newbury Park, CA

Design, fabrication, simulation and test of Interface cards and custom cables for an aircraft test system for Lockheed.

12/2010 to 8/2011 Teledyne Controls. Newbury Park, CA

Design and simulation of Altera FPGA coding for a Data Loader for the

Boeing Aircraft Co.

>FPGA used was an Altera Cyclone III.

>FPGA code written in Verilog.

>Modelsim for FPGA simulations

>Altera design tools under Windows

8/2009 to 9/2012 Northrop Grumman Woodland Hills, CA

Designed and developed a low power FPGA Controller for an R&D MEMS Silicon Accelerometer (cantilevered micro silicon beam).

>Actel Igloo-Nano device programmed with Verilog.

>Prototype PCB capture and layout first with EAGLE and then CADSTAR

>Actel design tools under Windows

>Modelsim for FPGA simulations

3/ 20012 to 8/20013 Northrop Grumman Woodland Hills, CA

Developed a low power FPGA Controller for an R&D NMR (Nuclear Magnetic Resonance) single axis Gyro.

>Actel Igloo-Nano device programmed with Verilog.

>Prototype PCB capture and layout first with EAGLE and then CADSTAR

>Actel design tools under Windows

>Modelsim for FPGA simulations

2/2009 to 6/2009 Advanced Motion Control. Camarillo, CA

Wrote the software (in C+) for microprocessor control of a fan motor. Commands are received via a standard CAN bus. Developed Prototype PCB for test.

>Microprocessor tools used: Silicon Labs C8051F500 IDE and Keil C+ compiler.

>PCB capture with OrCAD and layout with PADS.

8/2006 to 2/2009 Aerovironment, Inc. Simi Valley, CA

Programmed a Xilinx Vertex IV FPGA for real-time video functions for small Remotely Piloted Air Vehicles. The sensor was a high resolution CMOS video camera. Designed a prototype PCB for a miniature Hi-Rez CMOS camera. The application involved implementation of an I2C bus for camera control functions and a high speed serial link (SerDes) for high speed camera data transmission.

>utilized both Vertex 4 and Spartan families of FPGAs

>High Resolution Micron CMOS Video Sensor.

>Used Xilinx IDE tools for FPGA development

>Modelsim for FPGA simulations

>Xilinx EDK tools

> PCB capture with and layout with Altium

Developed Software based Transmit/Receive DSP architecture for an FPGA based Digital Data Link (DDL) for communication between ground stations and small Remotely Piloted Air Vehicles.

>FPGA used was an Altera Cyclone III.

>The tools used were Altera DSP Builder with MatLab/Simulink.

>Modelsim for FPGA simulations

>Altera design tools under Windows

2/2006 to 8/2006 King Nutronics Corp. Woodland Hills, CA

Developed various battery charging systems for portable pressure gage testers

Required by the US Navy. This included PCB design for the various units.

>The design capture tool was OrCAD and the layout tool was P-CAD.

10/2003 to 1/2006 IAS, Inc. Highland Heights, Ohio

Developed a Laser Gyro Test Station to test and calibrate refurbished Honeywell Commercial Laser Gyros. The system consisted of 1.) A microprocessor based laser control board, with local software written in C+. 2.) A real-time target (laser) control FPGA programmed with VHDL. 3.) AN RS 422 communications link to a process control PC. 4.) A Process Control Program (in the PC) written in LabView.

>The Board design capture tool used was OrCAD.

>The Board layout tool used was P-CAD.

>Actel AP600 device programmed with VHDL.

>Actel design tools under Windows

>Modelsim for FPGA simulations

9/2006 to 12/2006 EON Instrumentation, Inc. Van Nuys, CA

Developed low-cost, small outline power supplies for military applications. Performed both the electronic designs and the PCB designs.

>The design capture tool was OrCAD and the layout tool was P-CAD.

9/2003 to 12/2005 Southwest Sciences Corp. Santa Fe, NM

Developed low-cost, small outline, low weight, and high throughput DSP processing systems for balloon launched testing of the atmosphere. Core processor was the TI TMS320C6411. Responsible for PCB design and layout.

>The design capture tool was OrCAD and the layout tool was P-CAD.

>Actel AP600 device programmed with VHDL.

>Actel design tools under Windows

>Modelsim for FPGA simulations

7/1998 to 1/1999 Indigo Systems Santa Barbara, CA

Developed interface for a proprietary Low Resolution Infrared Video Sensor for Night Vision Application. This design included the following characteristics:

Interface Mechanized in single Xilinx FPGA.

Data Flow, Pipelined, DSP Functions Mechanized in FPGA

High Speed Concurrent Processing, 60 Frames per second interleaved.

Gate level mechanized "Bad Pixel Replacement" and "Smoothing Function" (expand 160 pixels/line X 120 lines to 640 pixels/line X 480 lines) algorithms.

>Used Xilinx IDE tools for FPGA development

>Modelsim for FPGA simulations

6/1997 to 3/1998 Photobit La Crescenta, CA

Developed high speed CMOS Video sensor interface designs for test and demonstration of Photobit’s proprietary CMOS video sensors. The interfaces were Xilinx FPGA based.

The tasks Involved:

Specified, architected, designed, fabricated, assembled and tested printed circuit board test and demonstration fixtures for both the 512 X 386 pixel and 1024 X 1024 pixel CMOS video sensor arrays.

The fixtures operated at video rates (60 frames per second) and provided video processing capability on board.

The video sensors are located remotely (at the end of a > 5 foot cable).

>Used Xilinx IDE tools for FPGA development

>Modelsim for FPGA simulation

ADDITIONAL INFORMATION

For a list of additional employers, prior to that listed above, please see www.apkengineeringinc.com.

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