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Design Engineer Electrical Engineering

Austin, Texas, United States
May 31, 2017

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Dan Reents



Excellent written and verbal communication capabilities.

Skilled in the areas of Micro architecture, Verilog/RTL design, Verification, and FPGA based emulation of SoC/ASIC subsystems and IP.

Experience with designs for mobile devices, embedded processor nodes, memory sub-systems, mesh interconnects, Ethernet NICs, enterprise class storage controllers, and various acceleration hardware for firmware offload.

Proven ability to organize design efforts and to deliver results working closely with marketing, architecture, design, verification, physical design, and firmware teams.

Key technical contributor, team leader skills, self-motivated, and committed to project success.

01/2014 – Present Mangstor Inc. Austin, TX

Principle Architect / Designer

Responsible for the Micro-architecture, Verilog/RTL design, Verification, FPGA based prototyping, and Documentation, of multiple complex hardware modules for an enterprise class, SSD (MX6300) and follow on Storage controller SoC products.

Overview of specific deliverables:

Highly parameterized Compute node (Xtensa processor based) and common I/O node hardware design (RTL). Nodes provide highly efficient and flexible virtual memory queue hardware (H/W). Working closely with Firmware (F/W) engineers to define and optimize the H/W for targeted “control plane” tasks.

Common switching logic for Compute and I/O nodes supporting interconnection as a systolic array (ie. Mesh Interconnect) with H/W and F/W based routing overrides.

Shared memory nodes used for Compute node intra-communications with H/W based access locking scheme. Shared memory nodes also support both H/W and F/W trace capture with time-stamps for debug and performance profiling.

Main memory (DDR3) client sub-system with multiple H/W acceleration features

(read / test / conditional modification / write operations) with client feedback. Highly parameterized RTL code for quick adaptation to follow on SoC devices and 3rd party DDR interface IP.

Hardware accelerator machine for XOR functions and LFSR based Multiplication for RAID / Erasure code generation and object based storage features. Recent



05/2004 – 01/2014 Server Engines / Emulex Corporation Austin, TX Senior Member Technical Staff

Responsible for the Micro-architecture, Verilog/RTL design, Verification, FPGA based prototyping, and Documentation of multiple complex functional hardware modules for an industry leading multi-port 10G Ethernet, Converged Networking Adapter (CNA) family of integrated circuits (OCe14xxx). Overview of specific deliverables:

Embedded processor with memory auto-work-load and bank switching features tailored to the efficient processing of networking protocols. Worked very closely with F/W engineers to optimize performance and provide useful H/W and F/W debug.

Linked list based Transmit Connection Selector supporting connection coalescing 205 Winchester Drive

Dripping Springs, TX 78620


for up to 64K connections. Timer tick based scheduling supporting Quality of Service standards. Optimized performance by designing a local cache for fast connection state access.

On-chip Shadow Ring Manager module for Ethernet host ring Work Request Block

“fetch ahead” significantly reducing host bus latency and improving overall transmission performance.

07/01 – 05/04 Layer N Networks Austin, TX

Senior Designer

Responsible for the Verilog/RTL design and Verification for all L2 and L3 networking hardware functionality for an SSL offload 10/100/1000G Ethernet, networking security silicon device. Developed high performance modules, high-speed filters, and intrusion detection hardware to meet and exceed product requirements.

06/00 – 07/01 Intel Corporation (LAN Access Division) Austin, TX Senior Silicon / Systems Architect

01/98 – 06/00 Mosaid Technology / Accelerix Corp. Austin, TX Senior Design Engineer

06/94 – 01/98 Advanced Micro Devices (AMD) Austin, TX Silicon / Systems Architect




06/88 – 06/94 Compaq Computer Corporation Houston, TX Notebook PC System Design Engineer

Tools /


ModelSim (Mentor Graphics) Verilog Simulator

VCS (Synopsys) Verilog Simulator

Altera / Quartus 14.x FPGA design environment

Cadence Xtensa processor generator

Unit level test bench / test case development (Verilog); task based BFM coding, self checking / score boarding techniques

Clock gating control sequence design techniques for Low power operation

Clock Domain Crossing (CDC) design techniques

Pipelined control and data path design to achieve high throughput and shallow logic paths

Highly parameterized RTL where appropriate for design reuse


Skills /



Sytem Verilog and the UVM for constrained random test bench development

ARM Processors and related bus protocols (ie. AMBA, AHB, APB)

PCI Express

C, C++, Perl

Patents /


U.S. Patent # 6,266,715 Universal serial bus (USB) controller with a direct memory access mode.

U.S. Patent # 6,067,627 Core section having asynchronous partial reset.

U.S. Patent # 5,534,889 Circuit for controlling bias voltage used to regulate contrast in a display panel.

U.S. Patent # 5,455,907 Buffering digitizer data in a first-in first-out memory.

U.S. Patent # 5,561,384 Input/Output driver circuit for isolating with minimal power consumption a peripheral component from a core section.

U.S. Patent # 5,860,125 Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an async partial reset and an async master reset. Education 1984 - 1988 Bradley University Peoria, IL Bachelors of Science in Electrical Engineering

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