CURRICULUM VITAE
AMRUTA HARISHCHANDRA NAIK KLS’s VDRIT
H.NO. BF/2,First floor, Haliyal,
Sona Apartment,Income tax layout, Uttara Kannada.
Chandra Layout,Vijayanagar, Ph:974-***-****
Bengaluru -560040 . ac0k3m@r.postjobfree.com
OBJECTIVE:
To work for an organization which provides me the opportunity to improve my skills and knowledge to growth along with the organization objective.
EDUCATION DETAILS:
QUALIFICATION
COLLEGE/INSTITUTION
SPECIALIZATION
BOARD
YEAR
PERCENTAGE
10th
Janata vidyalaya,Dandeli
-
S.S.L.C
2010
84.8
12th
BNJ PU College,Dandeli
PCMB
PU Board
2012
65.68
B.E
KLS VDRIT
ECE
VTU
2016
55.26
SKILLS:
Electronic devices
Analog circuits
Digital circuits
Network analysis
PROJECT DETAILS:
Title: Implementation of three stage pipelining on FPGA.
Objective: Is to increase the number of instructions executed per unit time in microprocessor.
Role: Performed coding using Verilog language.
Published paper in International Journal for Scientific Research and Development TOOLS USED:
Xilinx ISE 14.7
FPGA kit
TRAINING ATTENDED:
Attended internship on “Digital Switching System” & “Wireless Communication” at RTTC, Mysore
(BSNL) during Jul 15.
PERSONAL DETAILS:
Father s name: Harishchandra S Naik
Mother s name: L Srimati
Date of Birth: 12-12-1993
Languages Known: Kannada, English, Hindi
EXTRA CURRICULAR ACTIVITIES:
NCC(National cadet corp) holder of A Certificate.
Won first prize in long jump at taluk level.
Participated in “AAKRUTHI” in a state level event named Aavishkaar. HOBBIES:
Badminton
Watching TV
STRENGTHS:
Quick Learner.
Flexible and innovative
Active participation
Helping tendency
Declaration
I hereby declare that the above information is true to the best of my knowledge and belief. Place: Bengaluru Amruta.H.Naik