RESUME

*/***, **** ******,

Ketharimangalam,

Enangudi (Post),

Nagapattinam-609701.

Email ID: ac0h2d@r.postjobfree.com

Mobile: +919*********

VIJAY.V

CAREER OBJECTIVE

A position as the Entry level Engineer, To excel the software/hardware professional and hold up a challenging position in corporate world through diligence and dedication and to ensure utilize my technical knowledge and soft skills to learn, grow and add value to the organization. TECHNICAL SKILLS

DFT Skills : Scan Insertion, Boundary Scan and ATPG. Tools : Cadence - Genus DFT legacy UI, Cadence – Encounter test, Cadence – Virtuoso, Model Simulator, Xilinx Design Suite, HSPICE.

HDL : Verilog HDL

Basic Knowledge in C Programming.

Basic Knowledge in LINUX Commands.

Basic Knowledge in TCL Scripting.

WORK EXPERIENCE

Organization : Semicon Technolabs.Pvt.Ltd.

Designation : Intern DFT Engineer.

Duration : May, 2016 – Oct, 2016.

PROJECTS UNDER SEMICON TECHNOLABS.PVT.LTD

PROJECT : Test Project 1,2,3.

TOOL : Cadence – Genus legacy UI, Cadence – Encounter Test. TEAM : 4 Members.

RESPONSIBILITY : Set up for DFT rule checks, Check DFT rule violation, Fix DFT rule violation, Scan insertion, OPCG insertion, ATPG generation.

ACADEMIC RECORD

Completed M.TECH (VLSI DESIGN) in SRM University, Chennai with the CGPA of 7.57/10 during 2014-2016.

Completed B.E (Electronics and Communication Engineering) in EGS Pillay Engineering College, Nagapattinam with the CGPA of 6.88/10 during 2010-2014.

Completed HSC in KGM Matric Higher Secondary School, Thiruvarur with the percentage of 60% during 2009-2010.

Completed SSLC in KGM Matric Higher Secondary School, Thiruvarur with the percentage of 70% during 2007-2008.

ACADEMIC PROJECT

.

M.Tech Project Title: “ASYNCHRONOUS DOMINO LOGIC PIPELINE DESIGN BASED ON DUAL AND SINGLE RAIL DOMINO GATES”

Description:

The main objective of this project is to introduce a design method of asynchronous domino logic pipeline. The latch-free design provides the benefits of reduced critical delays, smaller silicon area, lower power consumption and implemented asynchronous quad rail domino logic pipeline design by using 2 Parallel FIR Filter.

Tools Used : Model Simulator, HSPICE

HDL : Verilog

B.E Project Title: “SENSOR NETWORK BASED OIL WELL HEALTH MONITORING

& SMART CONTROL USING GSM”

Description:

The main objective of this project is to create a sensor network based intelligent control proposed for power economy and efficient oil well health monitoring. Automatic oil well malfunction diagnosis is one of the main features of our proposed system. Tools Used : Visual Basic 10

HDL : Embedded C

ACADEMIC ACTIVITIES

Published a Paper on “Ultra Low power Asynchronous Domino Logic Pipeline design based on Dual and Single rail Domino Gates” in the “International Journal of Control theory and application” Conducted by SRM University, Chennai. CO-CURRICULAR ACTIVITIES

In Plant Training: Embedded Software Development with KEIL C & Mobile Technology, at MATRIX ARC SOLUTION, Chennai.

Workshop: Wavelet & Sparse Signal Representation, at Vickram College of Engineering, Madurai.

COURSE COMPLETED

I had completed the courses of “ORCAD Designing and Implementation of Printed Circuit Board” PROFESSIONAL STRENGHS

Optimist.

Quick Leaner.

Good team worker and also as a good team leader.

Ability to balance and tackle any kind of situation.

Self-Motivated and Positive Thinker.

HOBBIES

Drawing

Playing Volleyball

Listening Music

PERSONAL DETAILS

Name : V.VIJAY

Father’s Name : T.Veeramani

Mother’s Name : V.Jeeva

Date of Birth : 20.12.1992

Marital Status : Single

Sex : Male

Religion : Hindu

Nationality : Indian

Languages known to speak & write : English, Tamil. DECLARATION

I hereby declare that all the above information are true and correct to best of my knowledge. If given an opportunity, I would perform to the best to your expectations. Date:

Place: (V.VIJAY)

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