KiranKumar

Cell: (901*******)

email: ac0eu2@r.postjobfree.com

OBJECTIVE

Searching for an opportunity to maximize my Physical design skills with well-organized and growing company.

PROFILE

-Good Knowledge of Physical Design Process NETLIST-to-GDSII using CADENCE Encounter tools.

SKILLS

Netlist to GDSII implementation and signoff for blocks, which includes Floor Planning, Power Planning, power network Analysis, Placement, Congestion analysis, clock tree synthesis, Routing, Signoff timing analysis.

TOOLS

Innovus, ICC II, ICC, EDI, Magma, PTSI, ETS, Star-RC, QRC.

LANGUAGES

TCL, VERILOG HDL

PROFESSIONAL EXPERIENCE:

Worked As a Assistant Professor at “J. B. Institute of engineering and technology”

Location : Moinabad Chevella R. R. District Telangana.

Division : Electronics and Communication Department.

Duration : July 2015 to January 2017.

Worked as a GRADUATE APPRENTICE at “Bharath Heavy Electricals Limited”

Location : R. C. PURAM, HYDERABAD

Work : Maintenance of Programmable logical controls (PLC) and Computer numerical controls (CNC).

Division : Electronics Department

Major role And Responsibilities:

Maintaining of Automated machinery which are controlled by logic designing as per industry standards by using PLC logic designing and controlling the machine through computer numerical controls CNC. Under electronics department.

Duration : 10th January 2013 to 09th January 2014.

This helps me to automate the machinery in industry instead of manual fetching the data from electrical signal to mechanical by using sensors.

PROJECT:

Name : BUS CONTROLLER MODULE

Frequency : 245 Mhz

Instance count : 140K

Technology : 65nm

Tool used : Cadence Encounter,ETS, PTSI, ICCII, ICC, Star RC, Magma..

Responsibilities : Complete PNR from Netlist to final routing which includes floorplanning, Timing Analysis, RC-Extraction, CTS and routing.

PROJECT:

Name: Design and Implementation of Hardware Efficient Algorithm for FPGA Based Robot:

The main idea is to implement the design by developing Hardware efficient algorithm for indoor environment that is to identify the static and dynamic Obstacles, finds the path without any collisions and reaches the destination. It is a sensor based construction of different geometric structures to develop autonomous robot navigation. It has ability to automatically determine collision free paths in the presence of obstacles it is an important one for a mobile robot. The design is shown to be space efficient and fits in a Field Programmable Gated Array (FPGA) XC3S500E-4-FG320 device.

TOOLS USED: XILINX. 13.4

LANGUAGE: VERILOG HDL

HARDWARE: FPGA’S SPARTAN 3E

EDUCATIONAL QUALIFICATION:

SSC from Jyothi Vidyalaya High School BHEL R.C.PURAM Hyderabad with 69%.

Intermediate in MPC from Narayana Jr College Kukatpally Hyderabad with 65.30%.

Bachelor of Technology in Electronics and Communication Engineering

Hyderabad Institute of Technology of Technology and Management Medak A.P with 62.24%.

Master of Technology in VLSI system design from B.V.Raju institute of Technology Narsapur Medak A.P with 74.69%.

Kirankumar M

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