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system verilog,ASIC design and verification,UVM

Location:
Binghamton, New York, United States
Posted:
May 19, 2017

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Pradeep Saravana Kumar Ramaraj

Binghamton NY 334-***-**** ac0edt@r.postjobfree.com www.Linkedin.com/in/pradeepsaravanakumar Skills

• ASIC Design and Verification

• RTL Design using Verilog and SystemVerilog

• Constraint Random, Directed Testbenches

• Coverage driven, assertion based Testbench

• Design and Simulation of CMOS circuits

• Synthesis of ASIC and FPGA

• Scripting in basic TCL

• UVM (basics)

Education:

Binghamton University, State University of New York, Watson School of Engineering and Applied Science Master of Science in Electrical Engineering, (GPA: 3.20/4.00) May’17 Amrita Vishwa Vidyapeetham, Coimbatore, India

Bachelor of technology in Electronics and Communication Engineering, (GPA: 3.17/4.0) May’15 Certifications

• “SOC Verification Using System Verilog” by Udemy

• “System Verilog Assertions and Functional Coverage” by Udemy

• “Learn to Build OVM and UVM Testbenches from Scratch” by Udemy Professional Experience:

Graduate Student Researcher, Binghamton University, NY Sep’16-present

• Designed an RTL Verilog based 32-bit single core MIPS pipelined(RISC) processor

• Developed Verilog code for 5 staged pipeline blocks supporting arithmetic, Data transfer, Branch and Jump Instructions

• Verified the functionality using System Verilog Testbenches including constraint random, directed and coverage driven test cases for various DUT modules.

• Design Tools/HDL: Questa, ModelSim, System Verilog, Verilog, EDA Playground Research Associate, Cyber Med Laboratory, Binghamton, NY Mar ‘16 – Aug ‘16

• Designed a hardware IP using VHDL to implement a convolutional network Architecture

• Verified the functionality by integrating it with the Microblaze processor, using the Xilinx Platform Studio

• Developed Software using C to send input from the microblaze processor to the Hardware IP

• Design Tools/HDL: Xilinx EDK Platform Studio, Xilinx ISE, VHDL, C Project Experience

FPGA based UART IP Core Design using VHDL Feb’17-present

• Designing a VHDL based fully functional UART protocol

• Bitstream is generated to work on the Basys2 FPGA and verifying the functionality by transferring signals using switches and Teraterm VT software

• Design Tools/HDL : VHDL, Xilinx ISE, Teraterm VT, FPGA UVM based Verification environment for AMBA-APB Bridge Jan’17

• Developed a UVM based verification environment for basic APB slave

• Designed Agent, Sequencer, Driver, Monitor, Configuration and Sequence generator components for the verification plan

• Established a successful communication between the DUT and the Verification Environment

• Design Tools/HDL : Questa, EDA Playground

ASIC Design of 16 Bit Carry Bypass Adder Using Dynamic Manchester Carry Chain Dec’15

• Designed the schematic and layout of basic gates using Cadence Virtuoso and Schematic Editor

• Developed the complete layout using bit-sliced approach, verified the functionality by performing HSPICE simulations and computed the worst-case delay

• Design Tools/HDL : Cadence Virtuoso, Schematic Editor, HSPICE RTL Design of pipelined MAC hardware May’16

• Designed, developed and validated Verilog code for MAC hardware and optimized using Synopsys Design Vision to operate at 125Mhz, automated the synthesis and optimization by writing basic TCL scripts

• Design Tools/HDL : Synopsys Design Vision, TCL, Modelsim, Verilog



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