SANGHMITRA JHA

**** ********* ***, **********, ** 513-***-**** ac09xu@r.postjobfree.com https://www.linkedin.com/in/sanghmitrajha/

EDUCATION

Master of Engineering in Electrical Engineering Expected December 2017

University of Cincinnati, Cincinnati, OH GPA: 3.60

Coursework- VLSI Physical Design, VLSI Design For Testability, Low Power VLSI Design, VLSI Design Automation, Advanced Microsystems Design, Sensors- based Embedded Systems, Effectiveness in Technical Organization, Quality Control

Bachelor of Technology in Electrical and Electronics Engineering May 2015

Manipal Institute of Technology, Manipal, India GPA: 3.87

Coursework- Digital Logic Design, Computer Architecture, Data Structures, Microcontrollers, Solid State Drives

SKILLS

Programming Languages: C, C++

Scripting Languages: Python, Perl, Tcl

HDL: VHDL, Verilog, System Verilog

P&R Tools: MAGIC, Synopsys ICC2, Cadence Encounter, Synopsys PrimeTime, Tetramax ATPG

Synthesis Tools: Synopsys DC/DCG (DFT and Power Compiler)

Simulation Tools: ModelSim, HSpice, IRSIM, Wave View

Platforms: Windows, Linux

ACADEMIC PROJECTS

VLSI EDA tool for Circuit Bi-Partitioning Spring 2017

Developed C++ code to implement Simulated Annealing algorithm to minimize the cut set for circuit partitioning.

Reduced the time complexity by using the heuristics of Kernighan-Lin algorithm.

Implemented efficient data structures and algorithms for better results.

Decreased the simulation runtime by 94% for heavy benchmark files of 50000 cells and 500000 nets.

VLSI EDA tool for Placement and Routing Spring 2017

Developed C++ code to implement placement and routing for the given cells and nets within a square area.

Implemented forced directed algorithm to obtain optimum placement of the cells.

Designed the routing for the cells using Lee’s algorithm and achieved 100% routing.

Used GDB commands for debugging and back tracing the errors in the code.

Design Synthesis and DFT of a Multicore design Spring 2017

RTL development, synthesis, netlist generation and DFT of a multicore design for minimum area timing constraint.

Coded scripts in Tcl to perform logic optimization, technology mapping and check for the critical path in the circuit.

Developed design for test logic by scan insertion and stitching the scan cells of different cores.

Generated test patterns to test the fault coverage using TetraMax ATPG.

Minimized the power consumption at Register Transfer Level and gate level stages using Power Compiler.

Performed static timing analysis (STA) using PrimeTime.

ASIC Design and Testing Fall 2016

Designed an ASIC chip for a 64-bit Binary Tree Comparator using 0.6um technology.

Performed logic design for integration of cell libraries into ASIC design.

Developed RTL coding in VHDL and checked for functional simulation.

Performed floor planning, placement and routing, clock distribution and tape-out for the chip in MAGIC Layout Editor.

Increased the testability of the chip by joining all the flip flops to form a single scan chain.

Tested the fabricated chip using HP Agilent Logic Analyzer.

Checked for all corner cases and fault coverage of the circuit.

WORK EXPERIENCE

Systems Engineer at Tata Consultancy Services Ltd. 2015 - 2016

Led a team of 10 associates to design database for package delivery system which included the records of product orders, warehouse details, delivery vehicles’ details and tracking of packages using the ETL tools.

Designed interactive databases for real time data from the package delivery system using Informatica.

Created business charts and graphs for analyzing requirements using Business Objects.

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