Engineer Design

**** ******** ********* #**

San Diego, CA ***** HAOWEI CHEN 734-***-****

*************@*****.***

EMPLOYMENT

Senior Hardware Engineer Qualcomm Inc. June 2012 - Present

• Working in the parallel PHY group on front end design including Architecture, RTL design and QA, including interaction with external hardware teams (Controller, PD, verification etc), software teams, SoD teams and methodology/flow teams

• Architected and RTL designed clocking structure for LPDDR4 high speed interface, DFT/BIST and power management logic for DDRPHY

• Experienced in FPGA design, writing FPGA-friendly RTL code and FPGA synthesis and compilation

• Managed to work on multiple projects, with different process technology

• Demonstrated ability in static timing analysis, power analysis, synthesis, CLP/CDC/PLDRC/FV check, etc

• Experienced in low power design, high speed and low latency data path design; proposed and implemented power saving plans for hardware that lowered static power consumption by 40%

• Participated in Destination Q rotation program, that rotated within RTL design, power, and implementation teams, gained vision across different functional teams Hardware Engineer, Intern Cisco Systems Inc. Summer 2011

• Participated in board level and chip level debugging, verification and troubleshooting for Cisco’s routing and forwarding processors; narrowed down the failures to specific components of the system of 5 different prototypes

• Introduced new working process that improved working efficiency of the team by 15% System Integration &

Verification Engineer, Intern Ericsson Spring 2010

• Completed 12 verification projects for WCDMA/GSM Radio Base Station products, 10 of which received highly praise from manager; demonstrated initiative in conducting extra tests

• Offered advice and guided the team to improve the quality and radio performance of RBS products by 20%

EDUCATION

Ann Arbor, MI University of Michigan Fall 2010 – Spring 2012

• M.S. in Electrical Engineering, with focus on VLSI design, May 2012. GPA: 3.7

• Graduate Coursework: VLSI Design, Computer Architecture, VLSI DSP Systems, Digital Integrated Technology, Logic Circuits Synthesis & Optimization, Advanced DSP. Shanghai, China Shanghai Jiao Tong University Fall 2006 - Summer 2010

• B.S. in Electrical and Computer Engineering, August 2010. Major GPA: 3.8 AWARDS

• 1st Place, AMD/Michigan VLSI Design Contest

Languages and Technologies

• Programming Languages: System Verilog, Perl, C/C++, Matlab, Java, Python

• Engineering Tools: Verdi, Spyglass, Synopsys Primetime, Cadence Encounter, Design Compiler, Conformal Low Power

• Fluent in English and native in Chinese

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