Pallavi EDUCATION Chirumamilla *** cpallavi**@ Pearl St, North gmail. Attleboro, __com ( 301) MA _377- 02760 3774 University SKILLS _M. B. RVR Tech, __Eng, & JC _Electrical __Electronics College of Maryland, and of and Engineering, Computer Communications College Engineering Park, Guntur, MD, Engineering AP, __USA India June __May 2015 __2017 Programming Operating Software RELEVANT _Computer Systems, Compilers Tools: __System Systems: COURSEWORK Languages: MATLAB, Design and Linux, Optimization, and Caffe, Windows C, Architecture, __C+ +_Tableau,, SQL, Secure Verilog, Cadence Microprocessor Operating Python, Virtuoso, Systems, __Java, based ModelSim, HTML5, Design design, JavaScript, Eagle, and Deep Synthesis Proteus, Learning, CSS, Drupal, Github, of Machine _Digital PyCharm, Systems Learning, Android Embedded Studio WORK EXPERIENCE Lab ACADEMIC _Joint • • • _Assistant Quantum Built resolution Working Designed PROJECTS __an Institute, experimental on __a to PCB designing control Breakout _University the FPGA _a multichannel __Direct board of system Maryland Digital for noise for Spartan Synthesizer. __the cancellation ion 6 __trap FPGA setup in _during a for Python testing __ion trapping. based the various _environment inputs with and nanosecond _outputs. July 2016 timing - Present Polynomial Layout Keypad Evaluating ACTIVITIES _Lightweight University University University University University • • • • • • • • • • • • • • • • • • and __Locked Used Tutor, Performed Programmed Designed Performed servo Accessed Used Training Developed Cracked Used Developed Developed Used Developed Created _Controlled of of of of of and __Schematic __Evaluation __Dataflow Maryland, Maryland, Maryland, Maryland, Maryland, __the the the the __motor Wiseguy down _Improving _unit _the __flat DICE DICE Kali __the layout _and a and a a the post Lock _usernames _to working dataflow quasi-tests _scheduling _Metasploitable _Linux the _the __Placement _(framework _DRC _Design _lock implemented _of College College College College College DSPCAD __layout Tutors, _Accelerator _and Arduino _webserver __for a synthesizable OS check 4-_the and schematic the prototype __bit actor simulation for to _Park, Park, Park, Park, Park, and security University _unlock and _Integrative Verilog _determine adder __and UNO _Cell, for _the design _passwords __the by allowing _MD, MD, MD, MD, MD, _a __building __LVS __CD _CD _(Branch for _the _exploiting _of Atmega328P) _APGAN implementation. Verilog of _USA USA USA USA USA using to _to _a (_a of of _door. __Layout _the Command _door _the 4-_DAT _DAT _Maryland, an __only bit unit __Representative, _for __Operating _the scheduling open _accelerator __implementation lock sample adder _sample _a __the _the versus _tests __spectre vulnerability and __system board _secure Metasploitable _Line College _with _for rate __running Schematic) _rate System __schemes Environment) template. _testing _for to _72 __HTTPS, _with conversion RVR&conversion _access polynomial _Park __NAND using version services _a _the 4x4 _for __JC _secure _run _login. _the functionality gates _the _College __testing. keypad. __for _application _on _3-framework Kali _in computations. digit _shell _in the the the Cadence Linux of Polynomial design. __passcode _Metasploitable _and _Engineering of using _OS. _for _mail __the Virtuoso. the application. __from _to _C. evaluation Verilog _work the __system. March _on __keypad implementation. __April _Nov. __Nov. _the __Sep. __accelerator. 2016 _webserver. __2016 2017 _2016 __2016 _and – __operate – _– _– __– April Dec. _May Dec. __Oct. 2016 2016 _2017 2016 _2016 the