Design Engineer Project

RAHUL R. TOLEY

**** **** **** **

Austin TX *****

Telephone: 512-***-**** (cell)

E mail: abzmtx@r.postjobfree.com

OBJECTIVE:

To work as a logic design engineer in a upcoming team as an individual contributor or a lead . To contribute

to the goals of the project in terms of planning/execution of high speed, low power, high performance

characteristics and to support the product through implementation, bringup and customer support.

TECHNICAL SKILLS:

Architectures: QDSP6(Hexagon),MIPS, DLX, IA32(P4,P6)

H/w Languages: VHDL, System Verilog, Verilog, CBV, iHDL, System C

S/w Languages: Perl, Python, C++(STL), C, elisp, shell scripting, awk, dc_shell,matlab

Tools: Synopsys DC, PC, VSS, VCS, Siloti, Debussy, FV tools (FEV, CBV, and SPECMAN)

+EDUCATION:

+ Graduated from Georgiatech with a MSEE with a focus on advanced computer architecture /parallel

computing/Multi core architectures, networking and security

+ Several Graduate level courses in advanced Math and Physics.

+Bachelor of Engineering in Electronics Engineering.

University of Pune, India (1992 1996)

PROFESSIONAL EXPERIENCE:

+ Qualcomm Inc (Feb 2007 to Date)

Hexagon (QDSP6). MicroArchitecture & Design of multi threaded, 16/32/64k D Cache + MMU + Ld

Store Unit for a inhouse processor . I worked as a design lead /microarchitect on the Load Store unit of an

level 1 D Cache which was 8 way set assosiative, supported coherency and Snoopy prototocol through

various generations of the processor contributing in the microarchitecture, design closure and bringup .

+ Intel Corporation: Jan 2001 Feb 2007

+ SilverThorne ( P6, 5 Watts, 1.6 Ghz) Owner of XAPIC design through arch definition to tapeout: XAPIC

is the Programmable Interrupt Controller and houses all the control logic to manage various types of interrupts

in a internal queue, their status and resolution. This is a low power IA32 architecture.

+UMA Graphics Cores (1Ghz)

Performance model building for the Data Access Port: Help build c++ library to adapt a generic functional

model into a performance model with various knobs and access points using VC++.

Authored Specification of the L1 Cache architecture . Goal was to help reduce area by compressing the

Miss logic by restructuring the Tag Ram and bypass logic before sending the Miss/Demand request to L2.

Wrote a miniature ISG in perl to generate kernels to test out execution unit for the Graphics Core.

+TEJAS (P4, 3.5 Ghz, 100 W): Jan 2001 to May 2004

Design and Verification of Integrated Test Controller, MicrobreakPoint Controller, Control Register Access Bus

Using verilog, dc_shell, Intel tools for Static Timing Analysis and Formal Verification. It also involved testing of

the various features in the block, and supporting full chip effort in fixing and validating bugs.

+Lucent Technologies, NJ, USA (as a contractor on a Motorola Project called Patriot/Rainbow)

(On contract from Astor Tech Corp, NY) May 2000 – Jan 2001

Design Engineer for converting an existing Viterbi Accelerator netlist into Verilog RTL, using

Verilog and Synopsys dc_shell

+Motorola Semiconductor, Tel Aviv, Israel

(Internal transfer from Motorola India to MSIL) Nov 1999 April 2000

Formal Verification for EBIF (external bus interface):

Wrote formal specifications and constraints using verilog and CBV

+Motorola India, Noida (SMART Microelectronics)

As a Design Engineer, wrote a verilog solution to monitor the cycles of EIM module

This generates cycles for the standard Peripherals like SRAM, Flash Memories, and ROMs etc.

+SGS Thomson (ST Microelectronics):

+July 1997 June 1999 (Noida, India, Grenoble’ France)

Design of peripherals like SPI bus, RS32 for ST7/ ST9 8/16 bit microcontrollers using VHDL, verilog, VSS

and Synopsys DC, Alterra EPLD synthesis and meeting timing.

+AWARDS:

+Received Special Performance Award for design of SCI7 in 1998 while working as a Design Engineer in ST

Microelectronics

+Numerous Spot awards on Tejas for quality service and meeting tight timing goals on the design.

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