harshi_gupta_m.tech_VLSI_design

HARSHI GUPTA

Email:-***************@*****.***

Contact No:-088********

STREAM: Electronics & Instrumentation Engineering (B.E.)

VLSI DESIGN & VERIFICATION ENGINEERING (M.Tech.)

CAREER PROFILE:-

Objective:-

Seeking a challenging and rewarding opportunity with an organization of

repute, which recognizes and utilizes my true potential while nurturing my

analytical and technical skills

Summary Of Skills:-

. Certified Advanced VLSI Design and Verification course from Maven

Silicon VLSI Design and Training Center, Bangalore, having an inborn

quantitative aptitude & determined to curve a successful and

satisfying career in the industry.

. Conceptually strong in industry Standard EDA Tools for Front-End

Design and Verification. Dexterous at RTL coding using Verilog and

Test benches in System Verilog and possess the domain of ASIC, FPGA

design flow and Digital Design methodologies, PLL, MOS physics, op-

amp.

. Possess sound Analytical, Quantitative Research and Problem-Solving

Skill and gained rich experience in Verification methodologies while

working on various projects during the academic.

. Effective team player with exceptional planning and execution skills

coupled with a systematic approach and quick adaptability.

VLSI Domain Skills:-

HDLs: Verilog and VHDL

HVL: System verilog

Verification Methodologies: Coverage Driven Verification

EDA Tool: Modelsim and ISE

Domain: ASIC/FPGA Design Flow,

Digital Design

methodologies.

Knowledge:

RTL Coding, FSM based design, Simulation,

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EDUCATIONAL CREDENTIALS

Certified Advanced VLSI Design and Verification course, 2012

Maven Silicon VLSI Design and Training Center, Bangalore

M.Tech (VLSI design), 2012

Banasthali University, Rajasthan (Renowned global woman

university) India

With 71% average marks

B.E. (Electronics & Instrumentation Engineering) 2009

Institute of Technology Management (RGPV Bhopal)

With 70% average marks

Class 12th from MPBSE in 2004 securing 68 % average marks

Class 10th from MPBSE in 2002 securing 73.3 % average marks

Projects Undertaken:-

Title Real Time Clock - RTL design and verification (VLSI)

HDL Verilog

HVL SystemVerilog

EDA Tools Modelsim, Questa - Verification Platform and ISE

Synopsis In this project implemented the Real Time Clock using

Verilog HDL independently, architected

the class based verification environment using SystemVerilog,

Verified the RTL model using SystemVerilog, Generated

functional and code coverage for the RTL verification sign-off,

Synthesized the design

Title Dual Port RAM - verification (VLSI)

HVL System Verilog

EDA Tools Modelsim, Questa - Verification Platform and ISE

Synopsis In this project implemented the Dual Port Ram using

Verilog HDL independently, architected the class based

verification environment using system Verilog, Verified the RTL

module using System Verilog, Generated functional and code

coverage for the RTL verification sign-off

Title SPI Controller Core - Verification

HVL SystemVerilog

EDA Tools Modelsim, Questa -- Verification Platform

Synopsis The SPI Controller Core is an interface between

wishbone compatible Master Device and SPI interface Slave

device. It supports variable length of transfer word and

the core can be configured for 1 to 32 bit, 64 & 128 bit.

It supports data latching and data transfer at both edges

of clock. This core can be configured to connect with 32

slaves. The SPI Clock frequency can be adjusted by

configuring desirable value in 32 bit clock divider

register. The SPI Core RTL is technology independent and

fully synthesizable. Architected the class based

verification environment using system Verilog, Verified the

RTL module using System Verilog, Generated functional and

code coverage for the RTL verification sign-off

Title Reducing power consumption of E-paper.

Tools Atlas and Athena (TCAD)

Synopsis In this project redesign the e-paper to reduce its

complexity.

Title Automatic railway control system

Tools Microcontroller

Synopsis Objective is to the distance that is covered by train is

measured by the resolution of wheel.

Industrial Training:-

. One month training in Centre for Research & Industrial Staff

Performance (CRISP), BHOPAL on PLC programming.

Description: studied about PLC circuit designing, switching &

programming.

. Industrial visit in Uflex Industry in malanpur, Gwalior.

Description: Studied the working of automatic control system.

Extra Curricular Activities:-

. Attended two days workshop on "Tanner Tools Pro-A Complete VLSI Design

Software" at Banasthali University, Rajasthan.

. Participation in a dance competition and Participated in University

fest.

. Learnt French at Banasthali University, Rajasthan.

. Participated in national level workshop on Digital system & VLSI

design in MANIT Bhopal.

. Participated in seminar on VLSI design & embedded systems "Chip-Focus"

in OIST Bhopal

. Learnt horse riding at Banasthali University, Rajasthan.

. Singing: Winner, state level singing Competition

Personal Details:-

Sex: Female

Father's Name: Mr. Harikant Gupta

Nationality: Indian

Marital Details: Single

Date of Birth: 27th May 1987

Contact Details:-

Permanent Address:

Fancy shoes store, Shyambihari shoe market, Ambah, Morena

(M.P.)-476111

Email Id: ***************@*****.***

Contact: 088********.

Personal Qualities:-

Pro-active focused, Self-Motivated, Eagerness to learn.

I hereby declare that the statements made in this application are true,

complete and correct to the best of my knowledge and belief.

DATE:

PLACE: PUNE HARSHI GUPTA

HARSHI GUPTA

E-1, KALAGRAM SOCIETY, PAUD ROAD, KOTHRUD, PUNE, 411038

Email: ***************@*****.***, Contact: +918*********.

I am submitting herewith my resume for your perusal and favorable

consideration for a suitable post in your organization.

A systematic, organized, hardworking and dedicated team player with

an analytical bent of mind with excellent academic credentials.

Certified Advanced VLSI Design and Verification Course from Maven

Silicon VLSI Design and Training Center, Bangalore accepted with the

latest trends and techniques of the field and determined to carve a

successful career in the industry.

I have conceptual knowledge of industry Standard EDA Tools for Front-

End Design and Verification.

Dexterous at RTL coding using Verilog and Test benches in System

Verilog and possess the domain knowledge of CMOS, PLL,ASIC, FPGA

Design flow and Digital Design methodologies. Equipped with sound

analytical, Quantitative Research and Problem solving Skills and

gained rich experience in Verification Methodologies while working

on various projects during the academic.

A hard working & talented individual, seeking a challenging job

which synergize my skills and knowledge with the objectives of the

organization. My prime goal is to understand professional

environment and capitalize on opportunities. Professionally I am

looking for an opportunity that will help me utilizing my skills.

Dedicated and focused individual, determined to add value to the

organization I work for, through my exceptional knowledge and

learning ability. Possess well developed communication skills with

reputation of unwavering accuracy, credibility and integrity.

The above credentials along with my enclosed resume make me ideally

suitable for apposition in your organization. I would appreciate an

opportunity for a personal interview.

Thanking you,

Yours sincerely,

Harshi Gupta

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