Design Power

Asit Ambekar

Austin, Texas ? 512-***-****

? ************@*****.***

SUMMARY

An accomplished Digital Circuit/Physical Design professional with 15

years of

industry experience and 8 successful tape out of server chips in various

systems

configurations.

. Strong background in custom circuit design, Memory Design and

Synthesis/LBS

. Ability to work with off site teams

PROFESSIONAL EXPERIENCE

IBM Corporation, Austin, TX

Circuit Designer Oct 1997 - present

Responsibility includes designing Customs, Memory Design, Hybrids and

Synthesized circuits for IBM's P and Z Processors in various technologies

including 22nm

Custom Circuits / Memory Design

. Strong background in custom schematics, cross section verification

work using Powerspice simulator on highly critical timing paths and

creating LVS/DRC clean PD in Cadence environment using IBM tools

o Familiar with chip design process - starting with cross section

work and macro design onto chip tapeout

o Worked in various custom circuit design teams for Power

processors starting on ISU circuit and the Global team for

Register File/Memory Design for Power 4 - the first dual core

and the first gigahertz server chips in the industry

o Have been an integral part of Register File/Memory Design team

working on scannable and non-scannable, single, multiport and

CAM arrays for different units

o Added emphasis on low power memory design using clock gating

. Work with cross-site and international teams on daily basis for design

work

. A keen learner with strong problem-solving and interpersonal skills with

an

efficient, goal oriented work style

Synthesis/LBS

. Led synthesis efforts on different units on various Power Processor

teams

. Led efforts to convert customs macros to hybrids to help reduce turn

around time to get macros ready for tapeout with similar or better

timing and power results

. Work closely with RTL and integration teams on block I/O, placement

specifications and implementation with floorplan optimization to

meet/enhance performance, route-ability.

. Experienced at problem solving various design debug tools for

schematic and layout verification, create RC extracted netlist for

multi corner static timing analysis, EM and noise fail debug with deep

dive skills to fix block, unit and chip timing including logic fixes

using VHDL.

. Worked with different clock and voltage domain blocks

. Worked on initial efforts of converting synthesized blocks to an LBS.

Leadership Activities

. Led efforts for verifying validity of global voltage and cross domain

voltage

connectivity using voltage translators on P and Z processors

. Mentored new hires from India team along with local teams and junior

designers to familiarize them with IBM tools and methodology

. Works closely with the EDA team on Methodology and Design Automation

. Highly motivated team player with excellent communication skills

Tools:

. Niagara and Mojave tools for layout verification

. UltraSim, Powerspice, other IBM internal tools for schematic-logic

verification, EinsTLT for timing takedown, Synthesis, Place and Route

. Familiarity with Lotus Symphony and MS Office tools

Programming:

. C, Assembly Language, Perl

EDUCATION

. Masters in Electrical Engineering 1997

. Texas A&M Kingsville

WORK ELIGIBILITY

US GREEN CARD Holder

REFERENCES

. Available upon Request

Contact this candidate