Vlsi(Vhdl, Verilog) Programmer & Trainer

RAHUL GOYEL

Address : **-* **** *****, *** MANDI, MUZAFFARNAGAR ( U.P )

Mobile No. : 964-***-****

Email : *************@*****.***

Position Applied : VLSI department (VHDL,VERILOG programmer)

Employment History

Since FEB'2012 : KAIZEN ROBEONICS RESEARCH PVT. LTD. (JAIPUR) as a

VHDL Programmer &

Trainer

Designation : VHDL Programmer & Trainer

Duration : FEB 2012 - present

Work description : Responsible for designing of VHDL codes for

different projects . I am doing work at

Xilinx ISE 6.1,10.1 with FPGA SPARTEN

3E FG320 kit .

Educational Background

Discipline/

Examination Specializatio School/colleg Board/Universit Year of %

n e y Passing

Electronics Apex Rajasthan

B .Tech and institute of Technical 2012 67 %

communication engineering & University

technology

Saraswati

Intermediate Science +Math vidya mandir U.P Board 2007 60 %

inter college

(mzn)

Saraswati

S.S.C Science vidya mandir U.P Board 2005 58 %

inter college

(mzn)

Projects & software :-

. 32 Bit Multiplier of floating points by use of VHDL at Xilinx 6.1

/10.1.

. Traffic light controller by use of VHDL at SPARTEN 3E kit by Xilinx

10.1.

. Digital clock by use of VHDL by Xilinx 6.1 .

. 16 bit microcontroller by use of VHDL by Xilinx 6.1/10.1.

. 16 bit ALU by use of VHDL at SPARTEN 3E kit .

. Vending machine by VERILOG at SPARTEN 3E FPGA kit by Xilinx 6.1,10.1 .

. Object collision avoidance robot by use of FPGA SPARTEN 3E kit .

. LED patterns of FPGA kit by use of delay program at FPGA SPARTEN 3E

kit.

. Power estimate for microcontroller, BCD multiplier projects by use of

XILINX POWER ESTIMATOR(XPE) for SPARTEN 3E and VERTIX -4, VERTIX- 6

kit .

College Summer Internship

Company : Cetpa Infotech pvt. Ltd.

Department : VHDL, VERILOG

Date : JUNE 2011

Skills

. Knowledge in Microsoft office applications.

. Projects at FPGA SPARTEN 3 E kit by Xilinx ISE 6.1, 10.1, 10.1 with

VHDL & VERILOG.

. Work at XILINX POWER ESTIMATOR for SPARTEN 3E and VERTIX -6 kit.

. Basic knowledge of C, Embedded C language .

Seminars presentation

Place : Apex institute of Engineering &

technology

Topic : VHDL

Date : 2012

Personal Details

Name : Rahul Goyal

Age : 23 years

Date of Birth : 2-MAY-1990

Nationality : Indian

Gender : Male

Marital Status : Single

Permanent Residence : Muzaffarnagar(U.P)

Hobbies : Play Indoor Games, listening to Music,

Bike riding

Declaration

I hereby declare that all the above information given by me is true to my

knowledge and belief.

Date:-

Place:- Jaipur

Signature: Rahul Goyal

Contact this candidate