Engineer Power

Chenran Lei

**** ******** ****., ***. #****, Dallas, TX 75252 – 469-***-**** – *******.***@********.***

OBJECTIVE

Analog & Mixed Signal IC Design / Test Engineer utilizing training and experience in Analog and Power

Management IC

EDUCATION

The University of Texas at Dallas, Richardson, TX May 2013

M.S. in Electrical Engineering, GPA: 3.273/4.0

University of Electrical Science and Technology of China June 2011

B.S. in Electrical Engineering, GPA: 3.33/4.0

ACADEMIC PROJECTS

10bit, 400MS/s Pipeline ADC Design with CMOS 0.25µm process

Designed a high-swing, fully differential op-amp with 75dB open-loop gain and 1.27ns settling time

Converted the differential op-amp into a 2.5b/s switched-capacitor residue amplifier with clock-

bootstrapped switches and switched-capacitor CMFB

Integrated all residue amplifiers into a full-fledged 10-bit, 400-MS/s pipelined ADC with ENOB of 9

bit

PV-based Energy Harvester Design with CMOS 0.35µm process

Devised an MPPT circuit that tracks the Maximum Power Point (MPP) of the PV-cell with input

power range from 0.1mW to 11mW and controller efficiency of 97% at MPP

Built an low-dropout regulator (LDO) to regulate the output of MPPT circuit

Pulse Width Modulation Controlled Buck Converter Design with CMOS 0.35µm process

Designed a two-stage op-amp and type II compensation network

Implemented a buck converter with switching frequency of 1MHz, load transient response time of

40µs from heavy to light load and power efficiency of 92.4% in heavy load and 89.6% in light load

Closed-loop SCPC Design with CMOS 0.35µm process

Constructed a closed-loop switched-capacitor power converter with conversion ratio of 2/5

Achieved switching frequency of 10MHz, load transient response time of 2.25µs from light to heavy

load and 7.4µs from heavy to light load and maximum power efficiency of 81.54%

Front-end Receiver Design of E-UTRA Band 11 with 0.18µm CMOS technology

Performed a system level analysis and determined block-level specifications

Built a single stage cascade LNA with gain of 21.2dB, noise figure of 4dB, IIP3 of 3.5dBm and power

consumption of 20mW

Implemented single-balanced Gilbert cell mixer with gain of 14.5dB, noise figure of 10.2dB and IIP3

of 9.5dBm

Built a cross-coupled VCO with output power of 6.4dBm, power consumption of 4mW and tuning

range from 1460 MHz to 1505 MHz

COMPUTER SKILLS

Hardware: Oscilloscope, Spectrum Analyzer, Time Interval Analyzer, Logic Analyzer, Network Analyzer

Software: Cadence Virtuoso, Calibre DRC/LVS, Synopsys, ADS, AWR, Modelsim, Simulink

Programming Languages: HSpice, Verilog, Matlab, C, C++

Volunteer Work

Prepared for 2013 Technical Symposium on AAEOY (Asian American Engineer of the Year) with CIE

(Chinese Institute of Engineers)

Visa Status F-1, OPT available from 07/01/2013 to 06/30/2014

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