Engineer Sales

PETER KARPINSKI abwova@r.postjobfree.com

**** ********* *****

Evergreen, CO 80439 Home: 303-***-****

Cell: 720-***-****

PROFESSIONAL SUMMARY

Eighteen years of senior level experience in integrated circuit full custom

analog / mixed signal layout and auto routing design implementation from

hierarchical floor planning through full chip verification to final tape-

out. Proven ability to introduce and integrate new chip design software at

major semiconductor firms worldwide in pre-sales and post-sales capacity.

TECHNICAL EXPERTISE

Field Application Engineer / Customer Sales Support

Developed and delivered software product demonstrations and presentations

to engineering design teams at most of the world's largest semiconductor

companies. Worked in concert with sales team.

Successfully completed customer benchmarks at all levels of IC design

hierarchy.

Managed license and software installations and short and extensive EDA tool

evaluations at customer sites.

Developed and delivered training, workshops and tutorials for new customers

and instructional update collateral for new features, major releases and

new process nodes down to 40nm to existing customers.

Provided telephone, email and personal visit technical support for existing

users and design teams throughout the world including maintenance of

software related bugs, fixes and delivery of temporary work-arounds.

Provided technical on-site support for a full range of mixed signal and

analog IC design tools including connectivity driven layout from schematic

and netlist, full hierarchical top-down floorplanning and bottom-up block

implementation design methodology, correct by construction, constraint

driven place and route (manual and automatic as good as hand-crafted)

interconnect. This also included design at device, cell, block, top level

chip assembly and chip finishing stages of the design process plus final

sign-off verification to tape-out.

Corporate Application Engineer

Mentored and trained junior AEs and sales support personnel.

Developed instructional materials and workshops. Trained marketing, sales

and engineering personnel.

Rolled out new release feature training to internal users.

Acted as technical liaison between R&D and the AE and sales community.

Research and Development Engineer

Created requirement specifications for new routing enhancements.

Acted as QA engineer, testing for software usability and predictability.

Developed and monitored regression tests for performance and tool failure.

Found and filed appropriate bugs and validated fixes.

Helped architect 3 mixed signal block implementation flows, Cadence Chip

Integration Flow, Pulsic's Unity chip design flow and Synopsys ICC to CD

flow.

IC Design Tool Experience

Schematic capture - Cadence Composer and Synopsys CD Schematic capture.

Layout tools-- Cadence VXL and Synopsys Custom Designer - connectivity and

constraint driven DRD.

Floor planning tools - Cadence Preview and Pulsic UniPlan - block size

estimation, block resizing, block placement, pin optimization, pin

placement for busses, differential pairs, shielded nets, channel

optimization.

Transistor, cell and block placer tools - VCP, SE, UniPlace - all

connectivity and constraint driven.

Interactive and auto routing tools - Cadence VCR / CCAR (IC Craftsman), SE,

Pulsic UniRoute, Synopsys Custom Designer Router (TeraRoute) - global

routing, power routing (pin to trunk, mesh), signal routing, differential

pair, shielding (parallel, tandem and coaxial), matched length, capacitance

and resistance, topology editor (Steiner and fromto), bus routing, EM/R

constraint driven routing. Max width wire striping, analog symmetry and

mirrored routing, area fill flood routing, design for manufacturing

consideration routing, inter-layer clearance, width-based spacing and PDKs

down to TSMC 40nm. Familiarity with some 28nm rules.

Verification tools - Cadence Assura and Synopsys Hercules and ICV.

Scripting tools, CCAR ascii do files, Pulsic Python scripts, and tcl

scripting.

PETER KARPINSKI PAGE TWO

PROFESSIONAL EXPERIENCE

SYNOPSYS INC., Mountain View, CA 2010 - 2012

R&D Layout Software Engineer

Handled duties including testing custom designer interactive and auto

routing software. Integrated interconnect automation with CD layout

system. Experienced using Hercules verification tools.

Launched analog constraint driven routing solution to major Japanese

customer and provided technical support resulting in the sale of 13 seats

of custom designer software.

Tested and enhanced new features and engaged in several customer

benchmarks.

Created and presented interactive and auto routing demonstrations and

training to customers.

PULSIC INC., Santa Clara, CA 2005 - 2009

Field and Corporate Application Engineer

Supported pre-sales and post-sales activities for customers using Pulsic

Unity custom routing, placement and floorplanning tools. Created and

delivered demonstrations of Pulsic products, trained customers in the use

of Pulsic Unity software, product engineer and test Unity chip design

implementation tools and managed customer benchmarks and evaluations.

CADENCE DESIGN SYSTEMS, San Jose, CA 1997 - 2005

Custom Core Competency Team Application Engineer

Supported pre-sales and post-sales of Cadence full custom chip design

tools, CCAR, VCR, VCP, Preview floor planner, Virtuoso layout editor,

chip integration flow.

COOPER AND CHYAN TECHNOLOGY, Cupertino, CA 1993 - 1997

Application Engineer

Performed quality assurance testing of Specctra printed circuit board

design and IC-Craftsman IC design software. Trained customers, authored

and delivered demonstrations, managed pre-sales and post-sales

activities, customer evaluations and benchmarks.

RIDGE DESIGNS INC., Boulder Creek, CA 1980 - 1993

President

Designed PCBs for the following Silicon Valley electronic companies -

Schlumberger, GenRad Test Systems, LTX Corp, Opcom, VMX, GTE Fiberoptics,

Atari, Apple, Incite, Stratacom. Full service PCB design, fabrication

and assembly.

EDUCATION

BA, Anthropology, Biology, University of California, Santa Barbara, CA

1 year graduate school in Secondary Education, University of California,

Santa Barbara, CA

MILITARY SERVICE

US Army Vietnam Veteran, Honorable Discharge

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