Project Design
Resume:
VAIBHAV SRIVASTAVA
CONTACT INFORMATION SUMMARY:
To seek a challenging career as a Memory Circuit designer where my
Email: knowledge can be shared, enriched and to become a successful professional
in the field of VLSI Design and to work in an innovative and competitive
*******.******@*****.***
world.
Mobile: OBJECTIVE:
To achieve a leading & responsible position in a highly " growth
oriented" & "future prospective" organization by nurturing my
Postal Address:
professional skills & diligence as a practical tool that bring value
to the the organization I get related with.
S/O I.C.Srivastava
VARANASI 221002
(UTTAR PRADESH)
EXPERIENCE: (1.8 years)
Currently working as memory consultant in Synopsys india for Zia
PERSONAL INFORMATION
Semiconductor Pvt. Ltd. (5 months).
Worked as Memory Circuit Design and Characterization Engineer
Date of Birth:
for Zia Semiconductor Pvt. Limited (1.3 years).
EXPERTISE LEVEL:
01 03 1987
Languages Known:
Worked on various aspects of memory design ranging from bitcell and
sense amplifier statistical modelling, critical path modelling, design
• English (Read, Write, Speak)
and simulations of various memory blocks like clock generators, I/Os,
• Hindi (Read, Write, Speak)
Decoders, etc.
SKILL SET:
Tools and Scripting : Eldo, hsim, Ezwave, Cdesigner, EMC ( Zia’s Char tool)
and Design Architect, Shell Scripting
Programming Languages : Cshell, perl
Operating Systems : Unix
Tools & Packages : MS Office (Word, Power Point, Excel).
Area of Interest : Memory
Educational Qualification :
Qualified GATE 2009
M.Tech (EC) : 76.76% from NIT J (in 2011)
B.Tech (EC) : 72.80 % from IET MJPR University, Bareilly (in 2009)
12th : 74.40% ( in 2003 )
10th : 77.40% ( in 2001 )
2
PROJECT DESCRIPTION
Project 1
Objective : SP SRAM Compiler Development
Tools : Eldo, Ezwave and EMC (Zia internal tool)
Technology : TSMC, 130nm
Words : 32 2048
Bits : 4 128
Mux : 4
Mask : Yes
Responsibility : Design and qualification of SP SRAM compiler.
Critical path modeling
Single Port SRAM Bitcell Statistical Analysis
1. SNM
2. Writability
3. Ion and Ioff, Ion/Ioff, Istandby, Ileakage
4. Flip time
Load Estimation and device sizing
Understanding and working with EMC char flow
Writing margins and its qualification
Writing timing definition and characterization
Setup hold qualifications
Pin cap estimation and calculation
.lib generation
Project 2
Objective : Design and Characterize two port register file
Tools : Eldo, Ezwave and EMC (Zia internal tool)
Technology : TSMC, 130nm
Team Size : 3
Words : 1024
Bits : 64
Mux : 4
Mask : No
Responsibility : Design and Characterize two port register file Instance
Load Estimation and design optimization
Stimulus generation and simulations
Writing margins and race conditions and its qualifications
Setup and hold measurement
Timing definitions and qualification
.Lib generation and data sheet generation
Project 3
Objective : Sense Amp Statistical Analysis
Tools : Eldo, Ezwave
Technology : TSMC, 130nm
Responsibility : Design and qualification of latch type balanced Sense Amp.
Sizing and reaction time optimization
Offset analysis for 0 and 1 cases
Mean shift
Sense reaction time and pulse width estimation
Output glitch analysis
Project 4
Objective : HPSRAM characterization
Tools : Eldo, Ezwave and EMC (Zia internal tool)
Technology : TSMC, 40nm
Responsibility : Characterization, simulation and qualification of single port SRAM
Generating Stimulus, ic files
Simulations under various loads and slew conditions
Understanding and working with EMC char flow
Writing margins and its qualification
Setup hold measurements
Writing timing definition and characterization
.lib and data sheet generation
Trend Checks
Project 5
Objective : Memory compiler integration and GDS and Spice netlist coding
Tools : EMC (mcCell, mcFram, mcLib Zia internal tool)
Technology : TSMC, 40nm
Responsibility : Integration of compiler timing and backend view
Spice netlist stitching
GDS tiling
Liberty file generation using characterized data
Liberty file generation using characterized data
Integration of .lib, datasheet, gds, spice and lef view for compilers
4
Writing timing definition and characterization
Project 6
Objective: Port smic 40ll compiler from tsmc 40lp compiler.
Tools: Synopsys tool, herculus for extraction, hsim simulator,cscope
Technology: SMIC, 40nm
Responsibility: Extraction of netlist from ported compiler gds to generate spfs.
Post processing of spf for plugin.
Ring oscillator analysis for smic40 and tsmc 40 models comparison.
Simulation: Instance characterization, generation and evaluation.
RM setting, bitcell analysis and sense amplifier analysis.
Synopsys compiler flow understanding
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