Project System

Email ID: - ****.********@*****.***

Mobile No: - +91-814*******

Professional Experience Summary

Experience:

Over all experience of 12 months in VLSI Front end design and

verification

Undergone Training in Verilog and System Verilog.

FPGA design flow from RTL design to bitgen xilinx tool flow.

Involved in Development of class based Arbiter verification in System

Verilog.

Involved in Development of Test bench environment for various projects

in UVM.

Knowledge of JTAG protocol.

Work Details: -

Currently Working Joining Date Overall Domain

Experience

QLogic India Pvt. 11th JUNE 2012 12 months ASIC Verification

Ltd.

Education: -

Year Degree Major Subject Institution Marks

Obtained/Gra

de

2007-201 B.Tech Electronics and JNTU - Hyderabad 70.18%

1 Communication

2005-200 Intermedia MPC Board of 86.80%

7 te Intermediate, AP

2005 10th SSC 85.16%

standard

Course: -

Certified In Course

Duration

PDC in VLSI from Sandeepani School of VLSI Design 4 Months

Technical Skills: -

Primary Skills Developing components of Verification Environment

like Monitor, Driver, and Scoreboard and Integrating

these components in Verification environment using

System Verilog and UVM.

Languages Verilog, System Verilog, understanding of UVM.

Development Tool Cadence NC-Sim, Simvision ModelSim, ISE integrated

s tool suite.

Projects: -

Project JTAG (Language - System Verilog, UVM)

Duration March 2013 - still going on

Role Developing Test Environment

Creating Test bench Environment in UVM to

Description Verify Industry standard IEEE 1149.1 JTAG,

with scoreboard integration.

Project SFP & GPIO Registers (Language - System

Verilog,UVM)

Duration January 2013 - February 2013

Verification by creating test environment

Role

Verified This register blocks by Developed

Description Test Environment in UVM with Agent, driver,

monitor, reference model, sequences and

scoreboard.

Project LED Registers (Language - System Verilog,UVM)

Duration September 2012 - January 2013

Role Developed Test environment and test components

in UVM. And written test cases

Verified This register blocks by Developed

Description Test Environment in UVM with Agent, driver,

monitor, reference model, sequences and

scoreboard.

Project Arbiter (Language - System Verilog)

Duration 10 working days

Role Arbiter DUT Verification using system Verilog.

Designed a class based environment to verify

the arbiter with reference model. Designed a

Description class based environment in system Verilog with

having interface, transaction, generator, bfm,

monitor, and scoreboard to verify 4 masters 1

slave arbiter.

Project UART (Language - Verilog)

Duration 7 working days

Role RTL design of UART Transmitter.

Designed a UART Transmitter works with

different baud rates, Verified UART Receiver

Description using Verilog and conducted loopback test with

different baud rates by flashing this code

into FPGA Spartan 3 by generating bitfile.

Harikrishna Aella

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