ABDULLAH AL OWAHID

Cell: 205-***-****

Email: abux9q@r.postjobfree.com, abux9q@r.postjobfree.com

Location: 5001 Convict Hill Rd, APT 617, Austin, TX-78749, USA

OBJECTIVE:

Entry level position in RTL design, physical design, circuit design, computer architecture, design for test, emulation or verification and validation. Available immediately.

EDUCATION:

M.S., Electrical Engineering, Auburn University, January 2010 - May 2012

B.S., Computer Science & Engineering, Chittagong University of Engineering & Technology, January 2001 - December 2005

WORK AUTHORIZATION:

F1-OPT. EAD card valid 07/18/2012 - 07/17/2013. Can be extended for 17 more months.

PUBLICATION:

Abdullah A. Owahid, Foster F. Dai, “A 41.264W, 3.33GHz Processor Datapath Using Current Mode Logics In 130nm CMOS Technology,” IEEE International Symposium on Circuits & Systems, pp. 2565 - 2568, May 20 - 23, 2012.

TECHNICAL SKILL:

- Cadence - RC compiler, SoC encounter, Virtuoso, Analog artist, Spectre simulation, Cadence layout XL, Assura for QRC, DRC and LVS.

- Mentor Graphics - ModelSim, LeonardoSpectrum, Design Architect, DFTAdvisor and Fastscan.

- Synopsys – dc shell, Design vision, VCS, Primetime PX and Nanosim.

- Miscellaneous – VeriLogger, MATLAB, MAGIC for cell based/manual layout, Keil for ARM cortex processor.

- Operating Systems – Linux - RedHat 7.1 and 7.3, centos 5, Ubuntu 9.04, 10.04 and Windows.

PROGRAMMING LANGUAGE:

C, C++, Verilog HDL, assembly - MIPS, x86, ARM. Linux shell scripts, Tcl/Tk, Perl, and MATLAB.

GRADUATE COURSE WORK:

VLSI design, Advanced VLSI design, Low power design of electronic circuit, Analog circuit design, Introduction to digital and analog IC design, Computer architecture, Embedded computing systems, Digital signal processing, Microelectronic fabrication and design, Linear system and control.

PRJOECTS COMPLETED:

- 128Kbit buffer with timing, placement, STA and routing optimization in cadence SoC encounter up to GDS2 layout in 1µm technology.

- Design of 16-bit microprocessor in RISC architecture and implemented in Altera FPGA.

- Analysis of power, glitch behavior, activity factor and total switched capacitance per vector in Nanosim for serial multiplier circuit and verification of 1/2aCV2f law using voltage scaling in TSMC 180nm technology.

- Comparison and analysis of internal, switching and leakage power obtained from synthesizer tool to power components obtained from Primetime PX providing activity information in VCD file generated by VCS for 100 random vectors and repeated for multiple frequencies to plot power components in Matlab graph.

- Scan chain insertion using DFTAdvisor in synthesized netlist and ATPG using Fastscan to observe fault coverage.

- Cell based manual layout/design in MAGIC for 4-bit counter.

- Design of 3-bit multi modulus divider (MMD) using 2/3 dual-modulus prescaler cell that can be programmed to obtain divide ratio from 8-15 based on input combination for low power high frequency synthesis using Cadence Virtuoso in SiGe 5AM technology.

- Pseudo-nMOS NAND, NOR and Inverter microelectronic fabrication in 5µm technology.

uCdragon board LPC2292 16/32-bit ARM7TDMI-S CPU using ARM assembly and C

- Implemented a stop watch using C - pressing reset sets it to 00:00:00, pressing S2 button starts the timer, pressing S2 again stops the watch while showing the time on LCD, pressing S2 again resets the time. Roll over after 59:59:99 and displayed in right justified upper corner. Also last name of student is displayed at bottom left corner.

- Implemented a RMS task scheduler - in a given deadline, only 1 out of 4 processes (P1-P4) can increment its variable (V1-V4) at a time (twice in a second) when pressed reset button. Four process names were displayed in 4 lines in LCD (upper left corner) along with their variable number. Process variable incremented until it was preempted by its allotted time and the next one (based on RMS schedule) will start. Also there were READY, WAITING and RUNNING states to keep track of processes. When no process was running then ran a “Background Program” that blinks the LED light.

- Solved ACM big integer sum problem that can add two numbers (could be 1000 digits each or more) in C.

- Designed Monte-Carlo simulation in C.

- Implemented an iterative algorithm in C language to compute value of ?.

RESEARCH:

Design of high speed Current Mode Logic processor using 130nm CMOS technology. Tool used – Cadence Virtuoso, Analog artist, Spectre simulations and Cadence layout XL.

- Datapath designed for 16-bit multi cycle processor in RISC architecture.

- Determined optimum logic levels, logic-1 = 2.8V and logic-0 = 2.2V and logic swing, ?V=600mV.

- Designed individual CML logics targeted for lowest propagation delay 15-30ps and simulated for input levels changes at 83ps in schematic and performed extracted layout simulation.

- Used CML logics in designing block level components of datapath and performed schematic simulation along with extra load capacitance to mimic post-layout simulation.

- Estimated critical path delay of each datapath components and provided 3.33GHz clock frequency to perform processor datapath simulation.

- Verified functionality of CML processor datapath at 3.33GHz, obtained power consumptions over the clock periods, estimated chip area and performance.

PROFESSIONAL MEMBERSHIP:

Student member - IEEE

EXPERIENCE:

1. Voluntary Graduate Assistant, Engineering Network Services, October 2012 - Present

- Remote support graduate students in running their job in compute cluster.

2. Graduate Assistant, Engineering Network Services, January 2010 - August 2011

- Linux shell scripting for testing of High Performance Compute Cluster (512 processor) at RedHat centos 5 platform for parallel programming simulations.

- Configured resource manager (Torque) and job scheduler (Maui) for running jobs on HPCC.

- Upgrading queuing policy according to need, resource management (core and memory) and defining number of jobs a single user can submit.

- Ran multiple Matlab and MPICH2 parallel programs on HPCC to observe performance and load balancing of existing queue.

For details please visit: http://eng.auburn.edu/admin/ens/hpcc/index.html

3. Tutor - Math, University of Texas, San Antonio, August 2009 - December 2009

- Provided Math support to Math undergraduate and graduate students at MathLab.

4. System Engineer, Huawei Technologies Ltd., May 2008 - January 2009

- Provided remote fault handling to telecommunication nodes using proprietary Huawei software.

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