Engineer Design

George M. Jacobs

** ****** *****, ******** ** ***64

508-***-**** + **********@*****.*** + linkedin.com/pub/george-

jacobs/24/406/13b

Summary

Semiconductor design engineering professional with extensive experience in

all phases of hardware design cycle. Effectively delivers and implements

complex architectures in today's deep sub micron technology. Success

record of many ASICs in existing systems delivered on time with a proven

track record. Core strengths in

Multimedia decoder architecture and RTL design and verification, ASIC and

design FPGA

IP/RTL modeling in C SOC modeling

Graphics and video processing Memory controller design, DDR

Embedded Firmware Windows system/platform debug

Technical Skills

Languages: Verilog, VHDL, C++, Perl, System C

Tools: Synopsys, Primetime, VCS, Formality, Clock crossing tools,

Xilinx tool suite.

Professional Experience

Analog Devices, Wilmington MA

Feb 2013-Present

Digital Design Contractor

Redesign of ultralow power MEMs 3 axis accelerometer. Verilog design,

design compiler for synthesis, STA and DFT. Cadence tools for building

gate models to be used for SPICE simulations.

AMD (formally ATI) Boxborough, MA

2005-2012

Senior Member of Technical Staff

Developed and designed multimedia strategies for next generation SoC

platform. Utilized detailed knowledge of multimedia IP blocks to model and

port IP to new architecture.

. Multimedia architecture for next generation SoC design. Performed

design and modeling of SoC QoS mechanisms in System C and RTL to

implement a new chip infrastructure. Created top level design for

multimedia IP transition to SoC.

. Wrote RTL model/IP of new SoC infrastructure including traffic

generators, switch/node fabric, DRAM arbiter with priority modulation,

and IP DDR/DRAM controller.

Architecture, design, development, and verification of hardware video

decoder. Lead development of 5th generation video decoder hardware with

goal of 2-3x faster frame decode times.

. Lead architect for latest generation video decoder (UVD5). Redesign

of all H264 pipeline stages to achieve fastest H264 implementation.

Detailed design for RE (reverse entropy), IT (inverse), MP (motion

prediction), and CM (context management) blocks. Design target met of

2-3x faster than existing decoder. Modeling in C and Perl for

prediction of pipeline and firmware interaction to eliminate stalls.

. Video decoder C model design for verification and software team

support.

. Research projects:

. Use of compressed reference frame store, video decode.

. Hardware based multimedia post processing for power saving in

battery mode.

Design and system development engineer for UVD1-4. Lead system design

considerations for video decoder and managed chip bring ups through

several chip generations. Principle liaison in system debug with SW/Driver

team and diagnostics. Tasks included firmware design/team management, RTL

modification/design, power profiling, and performance analysis.

Lead RTL engineer UVD1 (Universal Video Decoder, rev 1), first iteration of

ATI full pipeline video decoder for H264 and VC1 codecs. Designed motion

prediction cache, DRM interface, interrupt handler and register bus multi-

master interfaces. Responsible for firmware and hardware bring up.

. Co-inventor "Video Decoder With Reduced Power Consumption and

Method Therof". File No 060121

George M. Jacobs

Page 2

TimeLab Corporation, Andover, MA

2004 - 2005

Senior ASIC Engineer

. Design and verification of high volume, proprietary technology clock

synthesizer targeted for use on Intel compliant motherboards. Novel

timing design based on free running loop and custom cells. Design

used proprietary algorithms to stabilize loop over voltage and

temperature.

. Designed test strategy into RTL and pattern generation using

Tetramax. This design required thorough knowledge of test issues due

to >15 clock domains and numerous custom cells. Design, unit test,

timing and formal verification for several ECO fixes.

Sandvideo, Andover, MA

2003

Principal ASIC Engineer

. Designed and verified a multi-protocol stream transport interface as

part of a 5 million gate .18u video decoder ASIC. The design

supported packet based transport and PES (Packetized Elementary

Stream) formats, and processed synchronization timestamps for timing

control.

. Designed a Xilinx XC3000 control FPGA supporting peripheral interfaces

including SPI, stream transport, host port, and video.

Trebia Networks, Acton, MA

2000-2003

Principal ASIC Engineer

. Generated architecture/design and performed verification for the TCP

Offload Engine (TOE) DDR memory controller as part of a 15 million

gate SNP1000 ASIC. Fixed and LRU type arbiters used to optimize memory

accesses. Gate level optimizations used to achieve the necessary

performance.

. Designed and verified a Xilinx control FPGA for early testing of the

qualification TCP offload engine. FPGA simulated interfaces to VLIW

processor as well as DMA, interrupt, and register interface functions

for a PC card system.

. Designed and verified a Xilinx FPGA for testing of the Fibrechannel

ASIC. FPGA supplied rings of posting/de-posting buffers, interrupt

control, credit management and DMA to Fibrechannel MAC.

. Named as inventor on a patent for improving noise immunity in DDR

memory systems. ( PAT 6,785,189)

Oak Imaging, Andover, MA

1998-2000

Principal ASIC Engineer

. Led a four-person design team to develop a 750K-gate Flat Panel

Control ASIC using VHDL, Synopsys Behavioral Compiler, and Primetime

tools. Project used many video algorithms including a (proprietary)

image scaling algorithm, brightness/contrast control, de-gamma LUTs,

OSD characters, and 3x3 pixel vector transformation.

. Redesign of Flat Panel Control ASIC, improving several aspects of the

original design. Ported original VHDL source to Verilog, added

RAMBIST, rewrote the top-level test structure. Created verification

environment in Perl and Verilog.

. Architecture and design of a Xilinx Virtex FPGA as an ASIC proof-of-

concept vehicle. Implemented frame rate conversion, picture in picture

and auto-adjust and optimized SDRAM memory accesses.

Number Nine Visual Technology, Lexington, MA

1997-1998

Principal ASIC Engineer

. Designed, synthesized, and verified the video pipeline for a 2D/3D

video accelerator. Designed a memory subsystem interface, video

format converter, and bilinear scaler and output color space

converter. The design supported generic YUV->RBB video formats with

all conversions in hardware.

. Designed and verified a monochrome/color animated cursor with a memory

subsystem interface. Wrote various tools in "C" to support test and

debug activities.

Additional Related Engineering Experience

Principle Engineer, PictureTel Corporation, Andover MA : ASIC/FPGA design,

board layout, analog design

Member of Technical Staff, Raytheon Company, Marlboro MA : FPGA design

Education

MSEE University of Massachusetts, Lowell

BSEE University of Maine, Orono

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