Engineer Design

SHASHIDHAR CHINTALAPUDI M No: +919*********

************@*****.***

**********@*****.**.**

Linkedin: in.linkedin.com/pub/shashidhar-

chintalapudi/23/44b/375/

Address: #**, *** ****, ******** ***ck, Banashankari -III Stage, Bangalore-

560050, India

Objective:

To obtain senior/Lead engineering position that utilizes my skills and

experience in digital hardware & programmable logic design and enables me

to make positive contribution.

Summary:

Over 9+ years of professional experience in FPGA based logic design and

implementation using industry-standard EDA Tools. Additional experience

includes Board designing, PCB designing and Board level to System level

debugging and testing

. Expertise in High speed FPGA based RTL implementation using VHDL,

functional verification, timing closure, debugging and board bring-up

. Expertise in Board level to system level integration testing

. Experience in high speed board design and PCB design

. Good experience in leading a team and work cohesively within a team

environment with accountability

Skill set:

HDL: VHDL, Verilog

EDA tools

Simulator: Modelsim

Synthesizer : Synplify Pro

Place & Route: ISE (XILINX), QUARTUS II (ALTERA)

Other tools: Xilinx' ChipscopePro,FPGA Editor

FPGAs: VIRTEX-2, VIRTEX-4, 5, SPARTAN-3,3E

CYCLONE-2 and STRATIX-2

Technology: TDMA and UMTS (3G)

PCB design tools: PADS and Allegro viewer

Test Equipments: Oscilloscope, Logic Analyzers

Configuration tools: Rational Clearcase, DCT

Academic Profile:

Education Institution/Univers- Main Subjects Class Month &

ity (Specializatio secured / Year of

n) % Marks Pass

SSC Z.P.S School/ Board Maths and 1st / Mar'1992

of Secondary Edu., Science 73.5%

A.P

D.E.C.E Govt. Polytechnic, Elec. & Comm. 1st / Sep'1995

MahaboobNagar/ 72.5%

SBTET-AP

A.M.I.E The Institution of Elec. & Comm. 2nd / Mar'2005

(Equalent Engineers (India) 56.2%

to

Engineering

)

M.Tech Visveshvarayya VLSI & 1st / 7.61 Dec'2009

Technological Embedded SGPA

University, Systems

Karnataka

Professional Experience summary:

> Working as Lead Engineer in Aricent Technologies Ltd., Bangalore for

ALCATEL-LUCENT's UMTS -3G-NodeB project (From July'2010 to till date-2

Years and 6 months )

> Worked as Lead Engineer and Senior S/W Engineer at SASKEN Communication

Technologies Ltd., Bangalore for ALCATEL-LUCENT's UMTS -3G-NodeB

project (From Mar'2006 to July'2010 - 4 Years and 3 months)

> Worked as Project Engineer at Wipro Technologies Ltd., Bangalore in

MSTC (Mixed signal Technology ASIC Center for wireless comm. of TI-

India). (From Sep'2005 to Feb' 2006- 6 months)

> Worked as Research Associate at CDOT (Centre for Development of

Telematics) in Wireless Transmission Division (From Oct' 2001 to Aug'

2005 (Duration: 3 years & 10 months)

> Worked as Hardware Engineer and PCB designer at Efftronics systems Pvt.

Ltd, Vijayawada, AP on Embedded Real time products (From Nov' 1996 to

Sep' 2001- ~5 years)

Key Projects summary:

Company: Aricent

Implementation of TOP (Transmit Overdrive Protection) feature on Core

Controller module for UMTS- NodeB:

One of the business critical issue affecting client a huge penalty for

every month. The Radio modules of UMTS-NodeB are breaking down due to

excess abrupt spikes of radio power. TOP is designed by radio

architects to protect the radio module from overshoots. The TOP

feature is implemented on FPGA of Xilinx's Virtex-4 on controller

module. This FPGA does the summation and routing of baseband radio

samples from modem to radio boards.

Responsibilities: Discussion with architects to understand the

requirements, feasibility study, DE (Development Estimation)

preparation, planning, guiding and partial implementation and tracking

the team for RTL implementation, testbench, functional simulation and

board level testing.

Synthesis and Timing closure for complex NECI FPGAs for MCRRH:

MCRRH is a Multi-carrier Remote Radio head which handles the Radio

functionalities like pulse shaping, rate conversion, DAC, ADC, down

conversion, rate conversion in RX and TX respectively. There are 2

complex NECI FPGAs called NECI1R and NECI2R which does the most of the

above functionalities. The FPGAs used are VIRTEX5 from Xilinx. This is

a multisite project and the design is done by Germany team, build

(functional testing and timing closure) by India (our team) and

testing by French team. Various stages of build deliveries are planned

for every 3 weeks with very tight scheduling.

Responsibilities:

Coordinating with design and test teams located in other countries

(Germany and France) to understand and sync-up for requirements,

scheduling, planning and delivery.

Guiding and helping the team to resolve critical issues in synthesis

and timing closure and delivered as per the schedule

Implementation of IQSL interface feature on FPGA to support new Modem

module:

A new Modem module is a high capacity, cost reduction Channel Element

module which does the Modem functionality on UMTS-BTS. To support this

new module a new serial link protocol called "IQSL" is developed. The

controller board need to support new module thus required the new

protocol. The FPGA (Virtex-4) on controller board which handles the

external interfaces implements this feature.

Responsibilities: Discussion with architects to understand the

requirements, feasibility study, DE (Development Estimation)

preparation, planning, guiding and tracking the team for RTL

implementation, testbench, functional simulation and board level

testing

Company: Sasken Comm. Tech Ltd

Implementation and delivery of ATM header corruption fix on controller

Module:

A critical field issue where a potential corruption of ATM packets

observed on controller board which causes quality degradation of the

NodeB system. After several weeks of investigation the issue

identified as ATM header corruption on interface between ATM switch

and HSSPC ASIC where FPGA provides data buffering between these two

devices. Further investigations confirmed that 1st byte of header was

corrupting and provided fix in FPGA by rebuilding the header by

looking into VCI field of the incoming ATM packet data.

Responsibilities:

. Investigation by field logs analysis, reproduction and debugging in

Lab

. Co-coordinating with other teams (S/W pltf-driver) and technical

discussion for fix identification

. Implementation of fix in FPGA and testing on board along with other

S/W teams

. Delivered the fix as per the schedule without any quality violations

Implementation and delivery of various FPGA features on different

modules of UMTS-NodeB

Implemented some features like Support of Repeater mode RRH, Fast PMM,

Slot2_11 swapping and Even-second enhancement AND STSR x+y on

different FPGAs on controller and Modem modules of UMTS NodeB.

Responsibilities:

. DE (Development Estimation) preparation that includes resource

estimation and planning

. Involving and guiding team on RTL implementing, simulation,

timing closure, testing and debugging

. Delivered the project as per the schedule without any quality

violations

Support and Bug fixing of UMTS-IBTS FPGA CRs:

Support and Bug fixing of the FPGA related CRs and enhancements of

different version of the controller and modem modules (boards) of UMTS

NodeB.

. Fixed critical complex CRs on xCCM, ICCM (2) and CEM modules

. Supported other teams in many CRs (over 1000 Nos) related to

XCCM, ICCM(2), xCEM and iCEM

. Developed new FPGA alarms on iCCM(2) boards to improve the debug

capabilities

. System level Hardware support to other teams

Company: Wipro Tech. Ltd

Vital Modeling for MSTC of TI-India:

MSTC is the Mixed signal Technology ASIC Center for wireless comm. of

TI-India.

RTL coding, Simulation and Vital modeling for different modules of one

of the MSTC ASIC.

Company: C-DOT (Centre for Development of Telematics)

Design and Development of Synchronization and Switching modules of

Enhanced Remote Switching Controller card (ERC):

Board and FPGA design and development of Remote Switching controller

card (ERSW) for C-DOT's Enhanced TDMA-PMP (Time Division Multiple

Access- Point to Multipoint) System which is a Digital Multiple access

Rural Radio (DMRR) system.

Responsibilities:

. High level functional specification and design document development

. Components selection and board designing

. RTL Implementation and functional verification for Switching

module and Targeting to ALTERA FPGA

. Involved and guiding the PCB design team for PCB design

. Board bring-up

Company: Efftronics Systems

Design and development of H/W module and system support:

Involved in various activities like hardware design, PCB design, board

level to system level testing and bring-up of various products of the

company like Data logger, Multi-color LED display boards, etc..

Responsibility:

. Design and development of digital stack card for interfacing

relay i/ps of 4096 no, board bring-up and testing.

. PCB designing of controller boards and stack cards of 4 layers

using PADS software

. System Integration and testing of individual Data logger system

and Networking of Data loggers.

. Field trial testing of the system in the Relay rooms located in

the stations.

. Successfully completed the System approval by RPIL (Railway

Products India Limited).

Note: Any system supplied to Railways to be approved by the

RPIL.

Contact this candidate