Design Engineer

Dandan Wang

San Jose, CA 1-312-***-**** *******@*****.***

OBJECTIVE: Full-time or contract positions in FPGA or ASIC design/verification with opportunity to

use skills in Verilog/VHDL, Tcl/Tk and C++ etc.

EDUCATION:

ILLINOIS INSTITUTE of TECHNOLOGY (IIT), Chicago, IL

M.S., Electrical Engineering May 2012

Emphasis: Computers and Microelectronics GPA: 3.81/4.0

DALIAN UNIVERSITY of TECHNOLOGY (DLUT), Dalian, China

B.S., Electrical Engineering July 2007

EXPERIENCE:

MOTOROLA MOBILITY, Libertyville, IL

Testing Engineer May 2011 – Nov 2011

Test newly designed cell phones from Original Design Manufacturer. Including test basic functions,

applications, RF signal response, etc.

SHANGHAI GM SHENYANG NORSOM AUTO COMPANY LIMITED. (SGM), Shenyang,

China

Maintenance Team-Leader July 2007 – May 2009

Managed work site safety and kept all equipment (PLC, Rectifier, Transformer, Motor, etc.) working

properly. Supervised set-up of equipment in new site project.

PROJECTS:

32-bit pipelined Processing Unit (CPU) implementation Nov, 2010

Developed a 32-bit CPU using Verilog programming language which consists of components of ALU,

memory, program counter, ROM, control unit and corresponding instruction set.

Verilog simulator Implementation Jan - May, 2011

Designed and implemented a Verilog-based RTL simulation software using C++, with lexical and

syntactic analysis, netlist construction and logic simulation functions included.

10-T full-adder low power consumption design May, 2011

Dual VT full-adder design using Cadence IC 6.1 tools for schematic entry, Synopsys Hspice for

simulation and Synopsys Nanosim for power analysis.

CAD Tool Design for Static Timing Analysis by using Tcl/Tk and C programming May, 2012

Designed and implemented a CAD tool for STA. Using Tcl/Tk for GUI and C for core algorithm.

Calculate arrival time, acquired time and time slack with delays input from GUI.

SKILLS:

Verilog/VHDL hardware description language

C++ programming language

Standard Cell (of VLSI) design of Schematic and Layout

Design and analysis with Cadence or Synopsys tools

Computer architecture and low power VLSI design

Tcl/Tk

ACTIVITIES:

IEEE, IIT Chapter, Since 2010

Bridges International IIT, President, 2011

External liaison Department Director of ECE Department of DLUT, 2008

Contact this candidate