Design Electrical Engineering

Devdatt Haldipur

**** ********* **, ***** ***** CA. Email: ********@***.***. Phone: 623-***-****

Summary:

A graduate student with masters in Electrical Engineering focussed on integrated circuit design, testing

and hardware verification. Have a strong background of digital circuit design and computer architecture.

Core competencies include:

• Design of Opamp and ADCs • Verilog Coding (Register Transfer Level)

• Digital Circuit Design and analysis • Physical Layout in Virtuoso.

Education:

Masters of Science, Electrical Engineering. GPA: 3.2/4.00 Graduation – May 2013

Arizona State University, Tempe, AZ

Bachelors of Science, Electrical Engineering GPA: 3.3/4.00 Graduation – May 2010.

Academic Projects :

Working on a spectre model of 12-bit fully differential RSD-based pipelined ADC at

80MegaSamples/second. [Cadence ICFB 0.25um process] – [Spring 2013]

Telescopic Cascode Differential Amplifier: [Fall 2012]

• Designed a telescopic cascade differential amplifier with wide swing cascade as tail device and

constant gm biasing.

• DC-gain = 65dB, UGBW: 50.2 MHz, PM: 68.2 and GM: 24.89dB, Load : 1pf

• Implemented in Cadence ICFB 0.25um process.

CMOS Beta-multiplier based constant gm current reference circuit : [Fall 2012]

• Optimized the circuit to achieve constant reference currents for wide range of VDD.

• Attained a percentage deviation of less 5%. Implemented in [Cadence ICFB 0.25um].

Design and Verification of Asynchronous Fifo: [ASIC Design] – [Xilinx ISE 13.0][May 2012 ]

• Designed a Fifo with faster Write Clock and a slower Read Clock without loss of any data. Used

overflow and underflow conditions to control the data being written on the Fifo.

• Tested circuits utilising random inputs to validate storage of data. Utilised FULL and EMPTY

signals to detect Fifo status. Insured Fifo worked for a particular range of entries.

• Wrote a system verilog code to test the system. Implemented scoreboard, mailboxes and interfaces

to create the testing environment.

Design of Engine Controller Unit for 12- cylinder 6 speed car in tsmc 0.25um process: [Cadence

0.25um] - [Spring 2012]

• Designed digital logic circuits to control the gear and cylinder functions and also to manipulate the

speed based on the motion of a car (Uphill/Downhill/Flat Surface Motion).

• Protocols for automation in car were given specifying RPM, Speed, gear, cylinder information for

each configuration.

Devdatt Haldipur

3131 Homestead Rd, Santa Clara CA. Email: ********@***.***. Phone: 623-***-****

• Circuits were optimised for speed and power. Schematic design and simulations were done with

Cadence virtuoso tool set. LVS and DRC check were performed.

Technical Skill Set:

Skills: Verilog, System Verilog, C/C++, MIPS Instruction Set, Perl, TCL, OVM and VVM.

Tools: Active HDL, Xilinx ISE 13.0, Cadence ICFB (layout, Extraction, LVS), SPICE, MATLAB.

Relevant Coursework:

Digital Systems and Circuits (EEE 425), VLSI Design (EEE 525), Advanced Hardware Design (CSE

591), Computer Architecture (CSE 598), Analog to digital Converters (EEE 527).

Contact this candidate