Project Design

RESUME

B.MAHENDRANATH REDDY Email id:************.******@*****.***

D/o :5/96-Upstairs,vijayanagram Street, Mobile

Number: 968-***-****

Proddatur,YSR District, A.P

Career Objective:

Looking for an opportunity to work with an Organization that offers

challenging assignments, to utilize my professional skill set and be dedicated

to work for increasing the reputation of the Organization.

Core Competency:

Good understanding of fundamentals of Transistors and circuit theory

Comprehensive knowledge of the methodologies and applications of advanced

verification tools

Good knowledge of Verilog RTL coding and Digitial Design Concepts

Good knowledge in verification methodologies and Testbenches in System Verilog

Good exposure to technology by undergoing additional training in VLSI

Good working knowledge of Linux, and C programming.

ACADMEIC QUALIFICATION

Post Graduation :- M.Tech in Vlsi System design at sri venkateswara

college of engineering and technology, chittoor with 82.3% in the year of

2012 afflicated to JNTU-A.

Graduation :- B.Tech in Electronics and communication and engineering at

vaagdevi institute of technology and sciences,Proddatur with 75.3% in the

year of March 2010 afflicated to JNTU-A.

INTERMEDIATE (M.P.C) completed at sri jaya sree Junior College in proddatur

with 94.1% in the year of March 2004-06.

SSC completed at Aditya high school, Proddatur with 88.16% in the year

of March 2004

Technical Skills:

HDLs :Verilog and VHDL.

HVL : SystemVerilog .

Verification Methodologies :Coverage Driven Verification,Assertion Based

Verification.

TB Methodology : OVM, UVM.

EDA Tool : Modelsim, Xillinx ISE Design suite, Questasim.

Domain : ASIC/FPGA Design Flow, Digital Design

methodologies.

Knowledge :RTL Coding, FSM based design, Simulation, CMOS

concepts,

Code Coverage, Functional

Coverage, Synthesis,

Static Timing Analysis. C

&DS, Basic OOPS.

Protocol Knowledge :MGC-ICPIT, FIFO, GPIO, UART.

Certification Course & Experience:

"Advance VLSI Design and Verfication Course" done at Maven Silicon Soft

tech Pvt. Ltd in Bangalore during the period of June 2012 to Nov -

2012.

Extra-curricular Activities:

Attend the course "Teaching Engineering using LabVIEW " at Sri

Venkateswara college of Engineering & Technology.

Attend a national level workshop on "VLSI & Image Processing" at Sri

Venkateswara college of Engineering & Technology.

Participated in a National conference at NHCE Bangalore on " Recent

Advances in Electronics & communication Engineering.

Project Details:

M.Tech Project High Speed Low-Power Viterbi Decoder Design For TCM Decoders

:

Description: In this project, VD is domaint module determining the overall

Power Consumption of TCM decoders. Here, a high rate

convolutional encoder are design and a pre computation

architecture incorporated with T-algorithm for VD, which can

effiectively reduce the power consumption without degrading the

decoding speed much.

Tools Used : Xilinx ISE 12.1, Xilinx XpowerAnalyzer

B. Tech Project The Impercepitlibie Video Watermarking Based On The Model Of

: Entropy

Description: In this project we have describe the video watermarking used for

digital copy rights protections. In this we are using the

concepts of model of entropy to acquire the motion of the

information. In this DWT transformation is used for to embedded

the watermarklog at the respective sideband.

Institute Real Time Clock . RTL design and verification

Project:

Description: Implemented the Real Time Clock using Verilog HDL

independently.Architected the class based verification

environment using SystemVerilog, Verified the RTL model using

SystemVerilog. Generated functional and code coverage for the

RTL verification sign-off Synthesized the design

Tools Used : Verilog. System Verilog.

EDA Tools: Xilinx ISE, MODELSIM

Institute MGC ICPIT - Verification

Project:

Description: The ICPIT provides a basic interrupt controller functionality

together with the capability to implement two timers which can

also be configured to generate interrupt. There are two timers

available, one is intended as a programmable interval timer and

the other as a watchdog timer. In the PIT count register and

count down .when it reach,it produce a time_out pluse, which

is one cycle wide and reload the count register value on the

next clock edge.

Tools Used : HVL: SystemVerilog, OVM methodlogy

EDA Tools: Modelsim, Questa -- Verification Platform

Title: GPIO - Verification

Description: The GPIO IP core is user-programmable general-purpose I/O

controller. Its use is to implement functions that are not

implemented with the dedicated controllers in a system and

require simple input and/or output software controlled signals.

All general-purpose I/O signals can be bi-directional The GPIO

IP Core has several software accessible registers. Most

registers have the same width as number of general-purpose I/O

signals and they can be from 1 to 32 bits. The host through

these registers programs type and operation of each

general-purpose I/O signal. Auxiliary inputs are used to

multiplex other on-chip peripherals on GPIO pins.

Tools Used : SystemVerilog, UVM methodlogy

EDA Tools: Modelsim, Questa -- Verification Platform

Personal Details:

Father's Name : B. Nagi Reddy

Date of Birth : 10-03-1989.

Gender : Male

Nationality : Indian.

Languages Known : English, Telugu, Hindi

Hobbies : Reading Books, Listening Music, Movies.

Permanent Address :D/No:5/96-upstairs, Vijayanagram street, Proddatur,

Kadapa (YSR)district, Andhrapradesh-516360

Declaration: I hereby declare that above information is true and written

with best of my Knowledge and belief.

Date:

Place: (B.

Mahendranath Reddy)

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