Design Project

RESUME

KAKADE MANJUSHA NARAYAN

E mail: ***********@*****.*** Viththal niwas, mursharpur galli,

Mobile: +91-879******* At Post Tal Ashti 414203,

CAREER OBJECTIVE

To be a successful professional and to utilize my skills to the optimum so that both my organization and I

are benefited by it. I want to work with a company that will give me opportunity to grow potentially, enough

challenges to let me be on the cutting edge of technology, and provide me all the support to perform

better than my abilities.

EDUCATIONAL QUALIFICATION

Technical Knowledge

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog

Experience in using industry standard EDA tools for the front-end design and verification

VLSI Domain Skills

HDL : Verilog, System Verilog, VHDL

Scripting : Perl

Verification Methodologies : Coverage Driven Verification,

EDA Tool : Questa Sim,ISE and Eoc encounter

Domain : ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge : RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage.

Professional Qualification

Vector Certified VLSI Design

From Vector India Pvt. Ltd, Hyderabad

Duration: October 2012-March 2013.

Project Details

1. uart

Universal Asynchronous Receiver and Transmitter

A UART (Universal Asynchronous Receiver/Transmitter) is the microchip with programming that

controls a computer's interface to its attached serial devices. Specifically, it provides the computer

with the Data Terminal Equipment ( DTE ) interface so that it can "talk" to and exchange data with

modems and other serial devices.

rtl coding simulation n synthesis

• EDA Tools: Questa – Verification Platform and ISE

• Team Size : 2

• Architected the design and described the functionality using Verilog HDL.

2. Library Management System using RFID (Major Project – Final Year)

Use of RFID Technology for library management like books management and keeping the records

• Team size : 1

• Duration: June 2011-june 2012

3. Low Power Consumption CMOS in VLSI (Seminar)

CMOS Technology is used in portable device to avoid maximum power consumption compare to

other logic families

• Team Size: 1

• Duration: Dec 10 – April 11

4. Water Level Control by using digital circuit (Mini Project – Second Year)

Control of water level of two tank used in society, indicate whether motor should on or off

automatically

• Team Size: 2

• Duration: Jun 09–Mar 10

GRADUATION

Board/ Passing

Examination Institute SGPA CGPA

University year

AUGUST

Semester- VIII 8.35 7.98

2012

Semester- VII NOV 2011 8.27 7.92

Dr. Babasaheb Dr. Babasaheb

Semester-VI MAY 2011 7.58 7.86

Ambedkar Ambedkar

Semester- V NOV 2010 7.41 7.92

Technological Technological

Semester- IV MAY 2010 7.59 8.04

University, University,

Vidyavihar, Vidyavihar,

Semester- III NOV 2009 7.83 8.19

Lonere, Lonere,

Semester- II MAY 2009 8.04 8.36

Raigad Raigad

Semester- I NOV 2008 8.67 8.67

AGGREGATE CGPA : 7.98

UNDERGRADUATION

Board/ Year of Perce

Institute

1 Level

University Passing nt

Class XII Residenshial junior College,Ahmednagar HSC Feb 2008 75.50

2 March

Class

Z.P.kanya prashala ashti SSC 85.86

2006

X

CAREER SKILLS

1. 1. Area of Interest vlsi designing and digital system Design

Languages : verilog, system verilog, perl, fpga,

2. Software Proficiency

asic

CO CURRICULAR ACTIVITIES

Summer Training Program on ”Embedded System and its Application” 2011

conducted by BRiCS in collaboration with Simplifix Automation & Solution Pvt.

Ltd, IIT Kanpur

Participated in X’celerate competition in National Level Technical fest 2011

CYNOSURE

Participated in LINE FOLLOWER ROBOT competition in National Level 2012

Technical fest CYNOSURE

EXTRA CURRICULAR ACTIVITIES

Chief Co-ordinator of ”Bharat Darshan” event held in college Dr.Batu 2012

Secured 2nd prize in Painting activity of annual social gathering event 2009

Passed the elementary and intermediate grade drawing examinations of 2003-2004

government of maharashtra with ‘B’ & ‘A’ grade

Certificate for meritorious performance in Maharashtra Talent Search 2005

Examination

1st prize in “Janiv Jagruti Spradha Pariksha” at state level by garvare 2004

community center,N-7 cidko,Aurangabad

PERSONAL PROFILE

:

Name Kakade Manjusha Narayan

:

Father’s Name Mr. Kakade Narayan Viththal

Mother’s Name : Mrs. Kakade Sunita Narayan

:

Date of Birth 21st Nov 1990

:

Sex Female

:

Marital status Single

:

Languages Known English, Marathi and Hindi

DECLARATION

I hereby declare that all details furnished above are true according to the best of my knowledge.

Place:

Date:

(Ms.Kakade Manjusha Narayan)

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