Post Job Free
Sign in

PCB DESIGN ENGINEER

Location:
Hyderabad, AP, India
Salary:
360000
Posted:
April 13, 2013

Contact this candidate

Resume:

g.pandu

CAREER OBJECTIVE

To further my career as Design Engineer that will utilize my organizational

skills, result oriented personality, analytical problem solving skills and

dealing with new technology that

has opportunity for advancement and learning.

SUMMARY

. Around 1.11+ years experience in Designing of Electronic Circuit

Boards right from the Schematic Capture, PCB Layout Design.

. Designed very high speed interfaces like SDRAM, DDR2, DDR3, SATA, USB

3.0, HDMI, ETHERNET, PCI, PCIe & JTAG.

. Exposure to communication protocols (I2C, SPI, RS232, RS485, I2S etc)

. Hands on experience in High speed board designs up to 18 Layers.

. Hands on experience on standard High Speed Digital, Analog & Mixed

signal Design.

. Worked with various memories like SDRAM, FLASH, DDR2 & DDR3.

. Familiar with test Equipments like Digital Oscilloscope and Digital

multimeter.

. Library builds according to IPC-7351, IPC 2221A and maintenance and

Bill of materials generation, constraint editions.

. Familiar in Routing with DFM, DFT & DFA.

. Generation of all documents for Design & Development.

EXPERIENCE:

Sr No. Company

1. Currently working with AIZYC TECHNOLOGY

(http://aizyc.com) Hyderabad since MAY 2011 to till

date.

SKILLS PROFILE

. CAD Packages Cadence - Orcad Schematic

Capture V 16.1, 16.3.

Cadence - Allegro (16.1, 16.3).

Mentor Graphics - PADS PCB LAYOUT 9.3.

Mentor Graphics - DX

Designer 9.3.

Mentor Graphics -

Expedition PCB.

Mentor Graphics -

Router.

Gerber Tools -

CAM350.

. Other IT Skills Ms Office Suite, Windows 9X, Windows 2K.,excel

EDUCATION

Jun '08 to May '11 B.Tech. (Electronics and Instrumentation

Engg.)

KMIT, JNTU University, Hyderabad, AP

Jun '05 to Apr'08 Diploma (Electronics and Instrumentation

Engg.)

Government Polytechnic college, Bellampalli

SBTET, AP.

Jun '04 to Apr '05 Board of Secondary School Education

Z.P.H.S, BOLLEPALLY.

Professional Experience

AIZYC Technology :

Designation : PCB Design Engineer

Company's Profile :

Aizyc Technology is a semiconductor design services and

SoC IP company. Available IP Cores - SDIO 3.0 Host & Device, USB 2.0 IP,

Ethernet IP + TOE, MIPI SLIMBUS. Services include Chip Design, Silicon

Validation, Physical Design, Firmware & Embedded systems development.

Brief on Projects Handled:

Project #1

Title: PLATFORM FOR RED DIGITAL CAMERA EPIC S35

Description of Work:

The Digital Still and Motion picture Camera is a modular

camera system that provides high quality video and audio for digital still

and motion picture applications. The camera system supports various

resolutions, frame rates, choice of recording media, and outputs for

monitoring.

Camera consists of blocks ISP, IOB and omap as the heart.

The following interface features are provided:

. Six 3.125Gbps four lane full duplex XAUI ports (3 ISP, 2 ISP/IOB

expansion and 1 Monitor expansion)

. Dual SATA with independent controllers

. Gen2 PCIe x4 controller with support for x1

. Gigabit Ethernet MAC with RGMII interface

. OMAP GPMC interface

. DDR3 x64 667/1333MHZ

. Slave SPI (internal AHB master)

. SDIO Host & Device

. 2 HDMI and 2HD-SDI ports (one shared monitor pipe)

. 16 GPIO

. UART

Number of layers: 18 layers

Position : PCB Design Engineer

Team size : 5

Duration : 4 months

Key Responsibilities:

. Footprint creation & verification

. Component Placement, Constraints setting

. Length matching of the high speed signals

. Routing, split plane & DRC error check

. Fabrication analysis, Assembly analysis, DFT & DFM generation

. Gerber files generation, Verification of Gerber files with Gerber

Viewers

Technology: Via on pads, blind vias and burried vias.

Tools : Orcad schematic capture V 10.3, Allegro 16.3 PCB editor

expert, CAM350 for

Gerber reviews.

Project #2

Title: USB3.0 Evaluation Board

Description of Work:

This is a high frequency board. This board operates at

5 Gigabit per sec. It has SPARTAN-6 FPGA from Xilinx, Gigabit Ethernet

Transceiver, 64MB Flash memory, 256KB EPROM, JTAG connector, SAMTEC

connectors, USB3.0 Type-B connectors, SD/SDIO device.

The following interface & protocols features are provided:

. Gigabit Ethernet Transceiver with GMII/MII interface

. JTAG interface

. PIPE+ULPI interfaces for USB 3.0

. Slave SPI interface

. I2C interface for EEPROM

. ABH BUS protocol

. Rs232 interface

. UART protocol

Number of layers: 8 layers

Position : PCB Design Engineer

Team size: 5

Duration : 2 months

Key Responsibilities:

. Footprint creation & verification

. Component Placement, Constraints setting

. Length matching of the high speed signals

. Routing, split plane & DRC error check

. Fabrication analysis, Assembly analysis, DFT & DFM generation

. Gerber files generation, Verification of Gerber files with Gerber

Viewers

Tools: Orcad schematic capture V 10.3, Allegro 16.3 pcb editor expert,

CAM350 for

Gerber reviews.

Project #3

Title: CPU Module

Project Details:

Hardware: LPC4350 Micro Controller, 256Mbit SDRAM MT48LC16M16A2P (16M16),

S25FL256S 32MBX2 SPI FLASH, 10/100T PHY KSZ8863RLLI, Stereo Audio Codec

CS4350,USB Type-A connector, USB Type-B connector.

Description: It is a high speed and analog signals board. The CPU module

will consist of a microcontroller, an EEPROM, an LCD, Keypad, RJ45 for

Ethernet, OBD connector for CAN, RS485 interface The function of the

microcontroller is to receive digital data via Ethernet and commands from

PC, program audio controls as per the commands and update the EEPROM.

Main features of microcontroller core:

. Standard I2C-bus interface.

. Two I2S interfaces: one input and one output.

. External Memory Controller supporting external SDRAM, NOR flash devices.

. Alpha numeric character display.

. General-Purpose Input/output (GPIO) pins with configurable pull-up/pull-

down resistors

and open-drain mode.

. Watchdog timer.

. Ultra-low power Real-Time Clock (RTC).

. 10/100T Ethernet MAC with RMII and MII interfaces.

. CAN controller.

The microcontroller contains an I2S-bus interface and provides a standard

communication interface for digital audio applications. The I2S-bus

specification defines a 3-wire serial bus using one data line, one clock

line, and one word select signal. The I2S-bus is interfaced to the digital

audio PWM/PA modules through buffer.

Number of layers: 6 layers

Position : PCB Design Engineer

Team size: 2

Duration : 2 months

Key Responsibilities:

. Footprint creation & verification

. Component Placement, Constraints setting

. Length matching of the high speed signals

. Routing, split plane & DRC error check

. Fabrication analysis, Assembly analysis, DFT & DFM generation

. Gerber files generation, Verification of Gerber files with Gerber

Viewers

Tools: Orcad schematic capture V 10.3, Allegro 16.3 pcb editor expert,

CAM350 for

Gerber reviews.

Project #4

Title: KRISTY EVALUATION BOARD

Description of Work:

The main intention of the project is to test USB3.0, SD

Host, Ethernet [1Gbps] and PCIe 2.0 Interfaces. It is a prototype board.

It includes interfacing of USB 3.0 transceiver (TUSB1310), USB 2.0

transceiver (ISP1504), Gigabit Ethernet transceiver (KSZ9021GQ), PCI-

Express PHY (XIO1100), 32-bit PCI Edge Connector, SDXC, SPI flash (M25P32),

EEPROM (CAT24C25) and RS232 transceiver (MAX3243CUI) with SPARTAN6 FPGA

(XC6SLX100/LX150).

The TUSB1310 is a single port, 5.0Gbps USB 3.0 Physical layer transceiver.

The FPGA interfaces to the TUSB1310 via a PIPE (16-bit wide operating at

250MHz) and a ULPI (8-bit wide operating at 60MHz) interface. The USB

connector interfaces to the TUSB1310 via a USB 3.0 SuperSpeed USB

Differential Pair (TX and RX) and USB 2.0 differential pair (DP/DM).

Number of layers: 6 layers

Position : Design Engineer

Team size : 5

Duration : 3 months

Key Responsibilities:

. Board Design

. Schematics Capture, BOM generation, Netlist Verification

. Footprint creation & verification

. Component Placement, Constraints setting

. Routing, split plane & DRC error check

. Fabrication analysis, Assembly analysis, DFT & DFM generation

. Gerber files generation, Verification of Gerber files with Gerber

Viewers

Tools: Orcad schematic capture V 10.3, Allegro 16.3 pcb editor expert,

CAM350 for

Gerber reviews.

Project #5

Title : HOME AUTOMATION

Description of Work:

Z-Wave is a wireless communications protocol designed

for home automation, specifically to remotely control applications in

residential and light commercial environments. The technology uses a low-

power RF radio embedded or retrofitted into home electronics devices and

systems, such as lighting, home access control and household appliances.

This is a 2 layer radio frequency board. It has ATMEGA88A

32-pin microcontroller with 8-pin EEPROMs, 18-pin Z-Wave module, 6-pin Z-

Wave programming connector, USB-Type_B connector, Battery charging circuit,

Battery monitoring circuit.

The following interface & protocols features are provided:

. UART protocol for microcontroller and Z-Wave module.

. SPI BUS interface for LCD & EEPROMs (128KB = 16K x 8).

. I2C protocal for battery monitoring section.

Position : Design Engineer

Team size : 5

Duration : 3 months

Key responsibilities:

. Board Design

. Schematics Capture, BOM generation, Netlist Verification

. Footprint creation & verification

. Component Placement, Constraints setting

. Routing, split plane & DRC error check

. Fabrication analysis, Assembly analysis, DFT & DFM generation

. Gerber files generation, Verification of Gerber files with Gerber

Viewers

Tools: Orcad schematic capture V 10.3, Allegro 16.3 pcb editor expert,

CAM350 for

Gerber reviews.

STRENGTHS

. Ability to communicate.

. Unquenchable thirst to become as info-rich as possible.

. Undying curiosity to delve into everything related to Science &

Technology.

. Learn ability.

. Taking Initiative, when necessary and being innovative.

. Excellent verbal and non-verbal communication skills.

. High levels of compatibility with human resources of all kinds.

. Ability to work in teams with all the odds involved in team-work.

. Adequate understanding of various aspects Information Technology.

PERSONAL INFORMATION

Name : Gangula Pandu.

Father's Name : Gangula Sathaiah.

Sex : Male.

Nationality : Indian.

Marital Status : Single.

Mail id : *****.*******@*******.***

Contact no : +91-995*******

Languages Known : English, Telugu and Hindi.

G.Pandu



Contact this candidate