Design Engineer
Resume:
M RUNAL INI .S. MUDL IAR
M OB : 096********
E -MA I L:
m ************@*****.**
Objective:
To work to the best of my abilities in a competitive environment and t ry to be as
i nnovative as possible for the progress of organization.
Specific Expertise:
1 Year and 8 months of experience in RFIC Design & Layout.
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Worked on Various EDA tools like Cadence (Virtuoso) and Advanced Design System tool for RF Design
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(schematic and layout).
Cadence Schematic, Virtuoso Layout.
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Academic Qualification:
SSC from Saraswati vidhayalaya, Nagpur(2005)
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Average percentage: (68%)
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Diploma(Electronics) from Datta Meghe Polytechnic, Nagpur(2008)
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Average Percentage: (79 %)
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B.E. (Electronics & Communication) from RTM Nagpur University(2011)
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Average Percentage: (67 %)
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Technical Proficiencies:
Work Experience at
Organization : SM Wireless Solutions Pvt.Ltd., sister concern of RFIC solutions Inc. (USA)
Period of Employment : July 2011 till Jan 2013
Designation : Circuit Design & Layout Engineer.
Website : www.rficsolutions.com
Worked & designed two stage Power Amplifier with Detector for frequency 2GHz – 6GHz on Win PS50 70
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Process 0.5um pHEMTProcess.
Worked & designed two stage Narrowband Power Amplifier with Detector for frequency 2.4GHz – 5GHz
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on Win PS50 70 Process 0.5um pHEMTProcess.
Worked & designed a Negative Resistance Oscillator for frequency 2GHz – 6GHz on Win PS50 70
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Process 0.5um pHEMTProcess.
Worked on Digital & Analog Layout for Various Processes along with DRC & LVS on Agilent design
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System (ADS).
Post Simulation on ADS.
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Layout on cadence
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Done visual analysis of dies.
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Customer Interaction.
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Cadence Schematic.
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Project:
Currently Working on Transceiver design on RFcmos 0.13um low power (lp) Process at frequency
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915.5MHz – 929.5MHz.
Responsibilities
Designed a flip flops, Latch circuit using gates, using RFcmos 0.13um lp Process.
Designed a 4 bit Shift register using RFcmos 0.13um lp Process.
Designing a 2bit & 4 bit frequency divider using RFcmos 0.13um lp Process
Designing Crystal Oscillator using RFcmos 0.13um lp Process for 26 MHz frequency.
Tool used:
Design: Cadence Schematic & Layout
IC Technologies:
WIN: 0.5 InGaAs pHEMT Process;
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TSMC: CMOS 0.18um and 0.13um.
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Software’s/Design Tool Knowledge:
Agilent’s Advanced Design System for RF Design(2006/2009)
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Cadence Schematic Virtuoso Layout Editor/Assure DRC for layout design /check.
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Mentor Graphic (Caliber) used for DRC & LVS Clean .
Technical Activities:
• MS CIT ( Maharashtra State Board of Technical Education)
• MS – OFFICE
• C Language
• C++
• Work in B.S.N.L for a week for industrial training.
• Or cad Workshop
• Course of 1 week on Microcontroller & Interfacing.
Extra curricular activities:
• I NTERMEDIATE Grade Drawing Exam ( Government of Maharashtra )
Participated in Entrepreneurship awareness camp.
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Participated in national level technical symposium “technorian ‘11’ ”.
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Personal Profile:
Name : Mrunalini S Mudliar
Date of Birth : 27/09/1989
Nationality : I ndian
Husband’s Name : Sai Sunil
Permanent Address : 8th cross,8th building
Chinnapanahalli, Bangalore 37
Languages : Tamil, Hindi, English, Marathi.
Declaration:
I hereby declare that the information furnished above is t rue to the best of my knowledge
MRUNAL I N I .S. M U DL IAR
Place: Bangalore
Date:
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