Anil Patel

****, ******** *****, ******, **-***59

512-***-**** ; abqxq7@r.postjobfree.com

Career Goal

Seeking a challenging position in Physical design, chip integration or CAD

design automation area.

Skills:

- Performing RTL to GDS physical design for high performance low power

designs.

- Driving tools and methodologies for High Performance & Low Power

designs.

- Driving 28nm - 90nm Technology (Libraries, Technology rules,

Memories).

- Project management, mentoring, P&R training and solving back-end

physical design issues.

- Floor planning, die size estimation, Power Planning, global signal

planning.

- Chip integration, partitioning and deriving timing budgets.

- STA timing analysis and timing closure with SI cross talk noise and

OCV/AOCV

- Implementing clock tree design and optimization. (CTS, Ccopt and

custom).

- P&R (place and route), DFM and MMMC timing optimization. (SOC

encounter).

- Interconnect RC extraction (StarRC, QRC).

- RTL Synthesis with DFT (scan insertion and ATPG coverage) and

Conformal LEC.

- IR drop analysis and power optimization.

MTS Engineer, Freescale/Motorola Austin (Aug99 to Nov2012)

Provided design services in performing RTL to GDS physical design using

Cadence tools (RC complier, SOC encounter, QRC, Nanoroute, Celtic, EPS,

ETS)

. Contributed to tape-out of several high performance networking CPU

chips, low power automotive chips, IMX tablet display block and Ruby

core. Designs were in 28nm - 90nm process.

. Performed RTL synthesis, conformal LEC, floor planning, power

planning, place and route (P&R), clock tree synthesis (CTS),

extraction, power analysis, SI cross-talk prevention, timing analysis,

timing closure and ECOs. Wrote SDC constraints. Performed spice

analysis to validate critical timing paths.

Developed physical design flows and methodologies using Cadence tools.

. Developed RTL to GDS flows using Tcl, Perl and Makefiles.

. Provided tools support, installed tools, regressed and distributed

design flows.

. Improved quality of design collaterals by improving accuracy of NLDM,

ECSM liberty views, optimizing cells from routing perspective,

optimizing technology rules, improving accuracy of abstract views

(lef, libs, cdbs etc)

. Implemented methodologies to improve designs from perspective of

power, DFM, SI cross talk, timing, spice analysis, Clock tree build

and multi-bus planning.

Cross function responsibilities.

. Managed project schedules, interfaced with EDA vendors and

contractors, evaluated new EDA tools and features, mentored other

engineers, gave P&R training classes, actively participated in

Freescale wide PD flow development and overlooked Back-end physical

design issues.

Chip integration for tape-outs of DSP SOC platforms and DSP cores.

. Performed chip integration of design blocks from block owners,

hierarchical floor planning (Chip Architect and DP), place and route

(Silicon Ensemble), top level routing (FlexRoute and Wroute), layout

editing (Virtuoso), timing closure (PrimeTime) and generating abstract

views (Silicon Ensemble and Apollo) for design re-use.

Sr. Engineer, AMD Austin (April96 to Aug99)

Place and routed DSP cores and Wireless design blocks. Responsibility

included, Synthesis (DC), Scan insertion, Timing analysis (PrimeTime),

Place and Route (Avanti Apollo), building clock tree, IPOs, ECOs,

extraction and physical verification (Calibre).

Developed and implemented a block timing system for K7 microprocessor based

on Pathmill. Acted as a consultant on Front-end Design Methodology. Played

a key role in improving ASIC design flow and evaluating new design tools

such as PrimeTime from Synopsys and BuildGate from Ambit.

Sr. Development Engineer, IBM Austin (Dec90 to April96)

Performed synthesis (bulldozer) and final timing analysis (Einstimer) for

Graphic chips in ASIC design group. Identified critical timing paths,

physical layout problems, and technology rules issues. Suggested logic

changes to improve timing. Played key role in development of bit stacking

macros involving logic design and physical layout.

Led the development of formal verification tool, BEC (Boolean Equivalence

Checker), written in C/C++. Developed and implemented various strategies to

verify custom macros required for microprocessor designs (Rios-2, 601, 602,

603, 604 and 620).

Developed, verified and maintained behavioral libraries for design

simulation (RS6000 and Power2 projects).

Quality Assurance Engineer, IBM Poughkeepsie (April89 to Dec90)

Developed qualification assurance plans for TCMs (Thermal conduction

module) used in IBM main frames. The work involved understanding the chip

and substrate failure mechanisms, drive corrective actions and make TCM

reliability assessment.

Product Engineer, IBM Fishkill (Mar85 to April89)

Developed Sentry Test Programs to evaluate chip specifications (8085, 8086,

MCS48, 8310). Designed stress circuit to assess chip reliability in terms

of failure rate and life of the chip. Designed and build test benches to

check the functionality of the chip. Developed chip specification.

Education

Bachelor of Electronic Engineering from Baroda, India

Master of Electrical Engineering from City College of New York (GPA 3.5)

Other Skills:

TCL, Perl, C, C++, HTML, C-shell, Assembly language, Intel ICE emulators,

Logic analyzers, EDS meter

EDA Tools:

SOC encounter, RTL complier, ETS, EPS, CTS, Ccopt, Nanoroute, QRC,

Virtuoso, DC, StarRC, PrimeTime, Pathmill, Avanti Apollo, Magma Tekton

Defensive Publication: Layout based methods to place and route scan-chains.

Reference: Will be furnished upon request

Contact this candidate