Physical Design, Timing Closure, Design for Test
Resume:
Ed Seymour
Advisory Engineer and Research Scientist
Austin, TX 78757
**************@*****.***
Summary:
Over 10 years of work in SOC RTL to GDS processing. Detailed work with RTL
synthesis including RTL updates for optimization. Timing constraint
generation and Static Timing Analysis (STA) along with timing closure by
way of route adjustments, VT adjustments and metal allocation as a form of
CTS. I have worked on clock distribution and delivery of ECO solutions.
Throughout this time I have also worked extensively on scan insertion and
ATPG. In pulling chips together for tapeout I have always been an
essential member of the team to ensure tapeout readiness. I believe
strongly in crisp communication and ensure effective teaming. I have also
debugged issues in libraries, technology files as well as routing.
Within my teams, I have always been a member of the review team to
formulate plans for upcoming chips and helped streamline design flows to
remove months of schedule. Among other tasks I have often beta tested new
versions of the flow to ensure they will work for the mainstream.
In low power management I have experience with clock gating, power headers,
power gating and IR analysis. I am an experienced user of P&R in Cadence
tools. In are area of signal integrity, I have done noise analysis and used
the results to drive timing and routing adjustments. I am also considered
to be a DFT expert and have patents for a couple implementations I have
used for test and defect identification. I am very well versed in
delivering DFT solutions that have no timing impact but provide high
quality coverage.
From technology node of 45nm through 22nm CMOS SOI, responsible for
discovering root cause on defects. In my most recent project, this began
with a task force assignment in 32nm and then I built the business case and
saw that a new project was completed in time for 22nm bringup to
demonstrate yield doubling 3 times in 6 weeks based on a new way of process
monitoring and testing.
Architected countless key CAD development projects which have reduced
design cycle, increased productivity and solved problems that could not be
addresses otherwise. These projects spanned my entire career and covered
flow automation, analysis, pin placement, defect detection, manufacturing
feedback, design-for-test as well as synthesis methods.
Extensive experience in using tools to implement them for SOC designs.
Considered by team members to be an exceptional problem solver with
excellent ability to convey and communicate findings and produce results.
Student of team dynamics, known for dramatic results with even diverse and
international teams.
Ten years of collaboration on VHDL and Verilog ranging from RTL though Gate
Level including synthesis, timing, constraint definition and checking as
well as place and route. Throughout this process, I advised synthesis
developers, helped create more effective design tool flows and illustrated
issues that helped streamline the design process.
1992-2012 - Advisory Engineer - IBM
Drove design cycle time improvements in 32nm and 20nm technology in
conjunction with detailed defect identification and elimination. This was
all based on detailed analysis of ATPG pattern results over several lots of
wafers. In the process, my analysis skills yielded root cause on several
defects essential to correcting process and changing designs to get early
user hardware functioning. This effort was based on data derived from
manufacturing test on patterns created within Cadence Encounter Test. It
involved correlation of fails across several lots of manufacturing.
Arrival a root cause was essential to doubling yield three times in the
span of two months. Called upon my years of direct experience with circuit
teams developing complex analog devices used in Phase Locked Loops, Efuse
circuits, onchip instrumentation, chip decoupling and power management
circuits, as well as, SRAM and Register File designs to yield processors
with over a billion transistors.
Led a team that was based in Austin with team members in Germany, Vermont,
New York and Austin. My leadership included early project planning and
process flow through detailed test analysis and pattern delivery. During
this period we also managed to move detailed test analysis into the RTL
realm which resulted in design cycle savings of 1 year.
Held the responsibility of top level pervasive design while helping define
top level chip connections for test. During this task, had to utilize chip
level make files to annotate the file dependencies.
In physical design of units, cores and chips, I have extensive experience
in Placement and Routing Tools and approaches. In terms of timing closure I
have experience with hierarchical and flat. I know how to create
constraints and validate them. In 45nm, 32nm and 22nm CMOS SOI as well as
the issues surrounding imaging of lines and the corresponding manufacturing
defects that can arise. I understand noise coupling and the impact on
timing. In terms of design sign off process, I am experienced in all the
final checks and fixing errors including physical checks, timing checks and
design for test.
Created scripts in Cadence Skill, perl, ksh and awk to parse data and
automate flows. I have a limited use of Tcl and a cursory use of Python.
Verification of voltage domain crossings during power up, validation that
circuits were designed to accurately pass valid logic conditions and
validation of logic fences were among my responsibilities along with
patterns for non-standard logic such as PLLs and other analog circuits.
Given the size of the die, responsible for defining a partial good strategy
to allow chips with between 4 and 8 working cores to be selected and
fencing of the bad cores confirmed.
Six years of Silicon Validation while running a bringup lab for the
Somerset Design Center in Austin and assisting customer bringup on location
in Italy and France. I also assisted in sponsoring firmware and 64 bit unix
kernel development.
1989-1992 Customer Consultant - IBM
Worked with Semiconductor Industry on process and device modeling then
Automotive Industry to change design flow for electronics at Jeep and Ford
Electronics.
1983-1989 IBM VLSI Academic Program Leader - IBM
Ran a university program on 4 University Campuses to teach undergraduate
students to design standard cell chips and managed joint research projects
as well as ensured student designs were manufactured and delivered in 12
weeks time on an aggressive schedule. This program was on University of
Illinois, Purdue, Penn State and Minnesota
1981-1983 Cad Tool Developer - IBM
Automated the process of assembling and submitting checking and analysis
jobs on microprocessor designs within IBM
Education
BSEE from Rochester Institute of Technology with a specialization of
Microelectronics
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