Engineer Design

SWATI M PATIL

A-***, Sector-**, Noida-****** Uttar Pradesh, India +91-999*******

***************@*****.**.**/*****.*****@*********.***

OBJECTIVE

A conscionable, highly experienced Senior IC Verification Engineer with Leadership Qualities acclimatized to work on

Multi Core System on Chip and Time Constrained Customer Needy Environment.

SKILLS PROFILE

- Strong SOC and partial IP Verification Experience i nvolving use of latest HVL’s ( SystemVerilog, System

Verilog Assertions, Verilog HDL, C, VHDL etc) with different Methodologies like SVBCL (Similar to

VMM/OVM) and URM

- Majorly Involved in Multi -core S oC Verification of Different IP’s and its Application Specific Interconnectivity

Checks and system level Performance Measurements.

- Dedicative for Customer Contentment and provide First Attention to All Kinds of Concerns

- Hands on Work Experience on Synopsys Tools (VCS), Cadence ( NcSim, IUS, and URM), Mentor

Graphics (ModelSim/Questasim), Xilinx, little on Magellan (Formal Verification) on Solaris, Unix/Solaris,

Windows and bash and tcl Scripts.

- Knowledge of Major Networking protocols Like PCIE (Rev2.0), SATA (Rev2.6), USB2.0 and USB OTG,

Ethernet and I nterfaces like SPI, GPIO etc. UART and DMA, Automotive Protocols like LIN and CAN

- Third Party(Synopsys) and Self coded VIP Integration and Verification at Soc +IP Level

- Effective Communication with Customer and Teammates

- Strong Level of Team Leadership qualities with System Verification Architecture Design and also have

good logical, analytical Skills to solve Problems

- Hardware - SystemVerilog(SVBCL, URM), SystemVerilog Assertions, Verilog HDL

- Tools - Synopsys, Cadence, Mentor Graphics

- Others - D atabase Administration & Version Control (DesignSync, ClearCase, Pi)

WORK EXPERIENCE

Soc Verification for OceanWorld (PCIE, DMA, Lynx25 and its Gasket) Jan11-till Date

- Targeted for Public Key or Security Management Application(Current Soc) and 3G LTE(Past Soc)

- Soc Optimization using SystemVerilog to make it Reusable Across Different Soc’s

- Verification of DMA & PEX(Rev2.0) Supporting X4/2/1 Mode with Speed using Lynx25 PHY

- System Level Performance Verification with different targeted application running in parallel like CPRI, SGMII

and PEX along with Toggle coverage closure for complete Soc Level Testplan for Integrity Checks

- Gate Level Verification(Zero+SDF), Production(VCD) pattern generation and debug support

Mentoring Team of 4 Freshers to ramp up on Soc Verification OnGoing

- Introduction to Soc Architecture and Verification Platform

- Training and discussion on Commo nly Used Basic I/F’s

- Presentation and sample run on testbench Structure, testing skills by introducing bug

- Support on Verification of different basic I/F’s level and block/Soc level Queries

Soc Level Random For Networking Soc Jan 10- Dec10

The project basically involves development system level random Env. With different master active on the bus putting

randomized transactions to check for the maximum bus usage. The protocols randomized include Etsec, Pex, TDM,

Esdhc, core with its UVP, and for the other masters we have used drivers just to check their system performance.

Different targets here include DDR, IFC, L2, PEX etc.

- Preparation of verification Plan w.r.t. SOC level requirements

- Random environment bring up on the initial releases and enhancement in env. w.r.t. new soc requirements

- Addition of random stims for different protocols and use of dummy drivers for some protocols like USB,

SAP, TPR, SATA etc to check their performance at main bus level

- Regression runs on every release and debugs failures for the new drop w.r.t. New soc level changes

- Regression runs on every new release with debug failure w.r.t. SoC changes & analyze coverage holes

for code & functional level and add/modify code/more scenarios/constraints to achieve maximum coverage.

Verification of SATA Controller in SOC Design with new Lynx18 PHY Jan 09-Dec 09

- Preparation of verification Plan w.r.t. SOC level requirements

- Simple, Medium and Corner case verification to check soc level performance covering basic protocol level

checking as well

- Regression runs on each release & debug failures for new drop w.r.t. New implementation at soc level

- Analyze coverage holes at wrapper/ip boundary level to achieve maximum toggle report

- Run Gate Level pattern on zero and SDF netlist and check for timing violations, analyze and report/get

approval from backend team, enable xfilters on synchronizer flops if required.

- Developing production pattern and debug them with test/validation team if required

Verification of RISC based QUICC Engine Protocols (Enet/SPI/UART/UTPOPIA) SOC Design

April 08-Jan 09

- Preparation of verification Plan w.r.t. SOC level requirements

- Simple, Medium and Corner case verification to check soc level performance covering basic protocol level

checking as well

- Regression run on every release and debug failures for the new drop

- Analyze toggle coverage holes at wrapper/ip boundary level to achieve maximum toggle coverage

- Run Gate Level pattern on zero and SDF netlist and check for timing violations, analyze and report/get

approval from backend team, enable xfilters on synchronizer fl ops if required.

- Developing production pattern and debug them with test/validation team if required

White box Verification of LIN 2.1 Master Design And Slave VIP Coding April 07-Mar 08

- Verification plan & coding Simple, Medium and Corner case verification to check design robustness

- Regression Run with code coverage and WhiteBox Checker for register to exercise every part of the code

- Verify those checkers in conventional as well in Specmen verification Environment

- Implementation of different verification components like Transactor, Sequence Driver and BFM

Verification and Debugging of USB OTG IP May 06-Mar 07

- Involved in debugging of the main core and ve rification of the IP

- Responsible for making Control transactions to work according to Specification

- Involved in verification of HNP and SRP Process

Verification of USB 2.0 Function Controller using Verilog System Verilog Assertions June 05-April 06

- Responsible for writing test scenarios and corner cases and Regression Testing

- Verification of the USB2.0 using Verilog HDL

- Writing testcases to check the different scenarios for different modes of Transfers

- Translation of checkers from OVA to SVA

- Worked on the protocol and extraction of the checkers

- Responsible for USB UTMI checkers

- Testing and Debugging of the USB UTMI checkers along with C overage Measurement

EDUCATION

- S.S.C. with 86.67% Maharashtra State Board (India)

- H.S.C with 86.57% in PCM Group Maharashtra State Board (India)

- B.E. (Electronics) in 2003 with First C lass from Shivaji University Kolhapur (Maharashtra, India)

- Advanced PG Diploma in VLSI Designs in 2004 from GCOEP Pune with A+ Grade

EXPERIENCE SUMMARY

- Currently working with Freescale Semiconductor India Ltd. as Sr. IC Design Engg. Since April 2008 till the

date

- Was working with Tata Elxsi Ltd . as Senior Engg. Since Mar 2007 to April 2008

- Was working with Silicon Interfaces as Assistant Engg-6. Since June 2005 to Mar 2007

- Was working as VLSI Research Trainee in NRT Technology PVT Ltd. since April 2004 to June 2005

INDUSTRIAL ACHIEVEMENTS

- Key achiever award in Silicon Interfaces for the verification and bug fixes for USB OTG project

- Renesas Work Appreciation for the verification on LIN 2.1 for critical time verification.

- Bravo For QE verification, Production and Silicon debug in Freescale s emiconductor

PERSONAL

- Handling Event Management Team in Freescale Semiconductor

- Active Member of Freescale Sports(Running and TT) group

- Completed Trek to Baali-Pass of height 5132mt in August 2011 in 5days time

- Completed Airtel Delhi Half Marathon in Nov. 2011 along with Biathlon and Triathlon

- Poetry writing

- Annual fundraiser for Children in Need Appeal

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