Engineer Process

FazlaRabbi Hossain

Email: *********@********.***

Address: ***** * ********** **

City: Queen Creek

State: AZ

Zip: 85142

Country: USA

Phone: 480-***-****

Skill Level: Experienced

Salary Range: $110,000

Willing to Relocate

Primary Skills/Experience:

See Resume

Educational Background:

See Resume

Job History / Details:

Fazla Rabbi M.B. Hossain

18560 E. Strawberry Dr. Queen Creek, AZ 85142 Ph.480-***-****, Cell.480-***-****

*****.*******@*****.***; *******@*****.***

https://www.linkedin.com/in/fazlahossain

Objectives: Seeking Process Integration, Process Engineering or Yield Engineering Position in Semiconductor Industry

Summary of Work Experiences

A responsible and organized Process Integration Engineer with 10 years of experience managing New Product Introduction in MEMS, Accelerometer and CMOS Micro-Controller. I also worked on the Power Management such as Schottky Diodes, TrenchFET & BJT. A knowledgeable and highly skilled Yield Engineer with over 5 years of experience in Schottky Diodes, Microcontroller, MOSFET, PHEMT, and HBT devices in Silicon, Silicon Carbide, and GaAs substrates. A dependable, organized, and hands-on Process Engineer with 8 years of experience in the area of Photo Lithography, Metals, Dry and Wet etch, and Diffusion processes. Identifies, prioritizes, and executes projects in support of critical product lines and related process issues in order to maintain >1.67 Cpk, yield improvement and increase gross margin, with management concern and appropriate customer input

* Excellent verbal & written communication skills and work ethics.

* Excellent leadership, engineering and technical skills.

* Works on complex product introduction issues

* Multi-tasking, self-motivated and Creative Technical Problem solving skills.

* Excellent product development and support skills.

* Review and sustain processing techniques and methods applied in the production and evaluate product lines accordingly

* Interface with design engineering, process engineering, and reliability engineering to address CQI (Customer Quality Incidence) and parametric issues with the product line performance and set goal to find the resolution

* Maintain strong customer relationship skills. Quality Product and on time delivery skills.

* Analytical, decisive decision making skills, and work effectively in a team environment.

* A good understanding of root cause analysis, FMEA, and Failure Analysis

* Effective innovator and successful technical problem solver of all critical process issues through research, design of experiment and development

* Certified Lean Six Sigma Green and Black Belt

* US Citizen

Summary of Accomplishments

* 15% yield improvement on 0.25um CMOS product line by changing Implant process.

* 500+ wafers scrap reduction by changing wet process integration.

* 3% yield improvement on another 0.25um CMOS Micro-Controller device by optimizing effective channel length (LEFF)

* 3% yield improvement and $500K cost savings on CMOS device by changing wet process integration from SuperQ to 100:1HF chemistry.

* 57% yield improvement on Schottky Diode by changing wet clean process.

* Successfully qualified 1200V, 150A SiC Schottky Diodes

* Successfully qualified 450 and 900kPa Pressure Sensor for Tire Pressure Monitoring System

* Successfully qualified 150V and 200V Silicon Schottky Diodes

Employment History and Responsibilities

1) Sr. NPI Product / Yield Engineer & Lean Six Sigma Black Belt Apr'10 - Present Freescale Semiconductor, Tempe, AZ

* Setup BOM of MEMS product (specially, TPMS) in Agile

* Implement control documentation such as Product Spec, BMY (Below Minimum Yield), SBL, DPAT. Review and updates them regular basis.

* Regular technical call with the external customers such as Continental Automotive System (CAS), TRW Automotive, and Beru

* Setup CMOS fab process flow and Oversee fab process flow of Piezoresistive Pressure Sensor

* Run Split Gate Flash ASIC process corner lot in TSMC fab in order to validate the new product flow introduction

* Monitor and review wafer probe data in three insertions as well as final test data for different temperatures (25C, 85C, -20C, 125C, and -40C) and perform statistical analysis using JMP software. Determine appropriate limits and variables for process or device specifications

* Perform LF characterization at different Sensitivity (High, Low, Very High) in different temperatures (25C, 85C, -20C, 125C, and -40C) between 2.1 and 3.3V supply voltage for two modes (Carrier and Data)

* Review and run correlation study of the major wafer probe bins with the critical PCM or SGPC parameters (Vt, Isat, Ioff, BV)

* Qualify new product per AEC Q101 guideline

* Lead and Perform failure analysis of CQI to find root cause

* Participate weekly technical call with automotive customers and address the quality issue & permanent corrective action through 8D format

* Write and present technical presentation and report to management and to the customer

* Create and Lead 8D, create Fishbone and find the root cause of the problem

* Champion on several yield improvement and cost reduction projects in assembly and in test

a. Recent yield improvement up to 12% on the major MCU product lines. These product lines were experiencing chronic yield loss for 4 years until I run correlation study and start DOE to find and solve the yield limiter issue.

b. Improvement of major bin reduction up to 83% of those major product lines

* Monitor process capability, Cp and process capability index, Cpk regular basis on critical parameters

* Coaching and mentoring several Green and Black Belt candidates

2) Sr. Device / Process Integration Engineer & Lean Six Sigma Green Belt May'06 - Apr'10 Freescale Semiconductor, Chandler, AZ

* Design and run DOE for the process and device in the fab

* Perform statistical data analysis of all DOE results and present report to the management

* Sustain CMOS Microcontroller Device fabrication that includes own process flow, monitor inline QBD, sustain class probe parametric and unit probe performance, maintain and improve ARIMA yield goal set by the department, review and maintain SPC on all class probe parameters, review and maintain SBL (Statistical Bin Limit) on all unit probe bins, maintain and improve BMY (Below Minimum Yield) calculated by Device owner twice per year

* Review and monitor several critical SPC charts of class probe parameters such as LEFF, WEFF, IDS, RCONT, KLVN and QBD. Update control limits based on the current end of line data

* Maintain six sigma methodologies in order to achieve >1.67 Cpk

* Lead team for any process driven issue that affects multiple lots and take necessary action such as tool constraint, run split lot and brainstorm to find root cause

* Monitor device related scrap, run tool commonality to find the suspect tool and take necessary action

* Monitor Bin Pareto and run ANOVA on the highest bin fallout to find the suspect tool and notify respective process and tool owner in order to take immediate action. Run ANOVA tool to determine the large F ratio to locate the stage that contribute huge yield loss and provide this info to the process team and tool owner to review in details and take necessary action. Review and notify any process deviation or tool malfunctioning based on the tool commonality data

* Support NPI business objectives that include NPI process flow, ensure product qualification, new product valuation, and achieve probe yield, and D0

* Lead and drive several process CAB changes for different phases such as evaluation, implementation, and closure

* Evaluate and run DMAIC project that show a cost savings more than $250K over the life of the improvement. Define and propose for change with the measurements, involvement in statistical analysis for implementation and close the project with the pilot run

* Communicates openly, clearly and honestly with all disciplines on the new product qual requirements, timeline on NPI CAB approval, closeout all pending issue before moving to the CAB approval for implementation

* Create and lead 8D for wafer scrap more than seven, process breakdown, continuous improvement that includes Team Charter, Problem Description, Immediate Containment, Root Cause Identification that includes Lab analysis and literature search, Define, Verify, and Implementation Permanent Corrective Action that includes split lot run followed by pilot lots and implementation, Prevent Recurrence and finally Congratulate Team Members

* For Process Breakdown, review the fail parameters and find the appropriate scribe grid process control structure or process control module for lab analysis. Send location map of the bad sample or structure on the wafer to the lab folks for x-section. Advice on how to do hand probe and which pad need to test to find the bad structure if it is RAM fallout or leakage driven, if functional or speed related then suggest to do photo emission to find the "HOT SPOT" using EMMI (Emission Microscope for Multi-Layer Inspection) or XIVA (Externally Induced Voltage Alterations)

* Review lab analysis report such as TEM, SEM, XPS, Auger, etc to determine the root cause and create report for the Device and Process community for initial containment and possible tool restriction. Review low yielding lot (LYL) and find correlation with the inline defect map and proceed to lab analysis to confirm the hypothesis.

3) Sr. Product / Integration Engineer Sep'03 - Apr'06 Diode Inc., Lees Summit, MO

* Very High voltage power Schottky diode development and yield enhancement.

* JBS and Dual Metal Schottky development.

* SiC Schottky diode development.

* Create and modify Schottky process flow

* Maintain customer test datasheet.

4) Lead Process Engineer Sep'01 - Sep'03 Cree Inc., Durham, NC

* Sustain in all Silicon Carbide (SiC) Process Areas (Photo-lithography, Evaporation, Sputtering, Wet and Dry Etch)

* Create recipe for the 790 Dry etcher

* Hands-on experience in Dry, Wet etch process, Metal Evaporation process

* Inspect wafers at every process steps. Perform final visual inspection before shipping.

* Rework documentation. Document all specs, recipes, process change and any process related problems.

* Run actual DOE in the tool and analyze data for any process change.

* Product documentation through internal network. Co-ordination from Starting material to the Package and Test.

* Developed 1200V & 150A Schottky Diode on 6" 4H-SiC & 6H-SiC material

* New part setup throughout the line.

5) Staff Process Engineer Dec'99 - Sep'01 ON Semiconductor, Phoenix, AZ

* Product Yield Improvement and Interface with Module Engineer.

* Data Collection and Statistical Analysis. Run DOE and collect probe data from our internal database and analyze using JMP statistical software to find the best Cpk and standard deviation.

* Compare result with the standard process and with the historical data. Present this data in Power Point format to the Process Change Action Board (PCAB) for process approval as well.

* Monitoring Probe Yield on several Schottky diodes. Finding yield limiters in the Probe, Process and Starting Material area. Troubleshoot device to know the failure mechanism and run commonality in the process to find the source of the problem.

* Evaluate different starting material vendor (like Sumitomo, Unisill, ATMI, Terosil) for cost reduction.

* PROBE SPEC Modification. Test program validation and release to production.

* Evaluate different top metal such as Au and Ag for all Schottky diodes to solve assembly issue.

* Evaluate post-metal anneal process for different barrier Schottky devices.

* Evaluate sintering process to reduce VF on certain Schottky devices.

* Interface with module engineer and generate DOE to resolve all process issues.

* Characterization of different front metal's evaporator. Evaluate Pre-Metal Clean Hood (10:1, Piranha, Solution B). Setup SPC for metal deposition. Beam Sweep Implementation. OCAP in every place of evaporation area. Evaluation of different Aluminum recipe for reduces cycle time as well as cost in process.

* Provide training for Operator and Manufacturing Associates. Sustain engineer in Cr-Ni-Au, Ti-Ni-Ag, Ni and Al process. Ensure the stability of various processes and develop a plan to calibrate equipment with maintenance group

6) Device Engineer Sep'97 - Dec'99 Motorola Inc., Phoenix, AZ

* Manage electrical distributions, Cpk's, scrap, quality, design and analysis of engineering experiment (full and fractional factorial) to improve device and process yield.

* Successfully improved CPK as well as yield from 30% to 97% of Schottky diode line.

* Run project for elimination of standard process steps to reduce process related scrap and cycle time.

* Set up device specification as well as shop order of standard process.

* Support QS9000 activities. Interface with and support new product development (NPD) team as part of cross-functional team activities.

* Research and Development on poly-silicon and tungsten silicide (WSiX) gate module for 10 times faster switching speed use in Trench MOSFET devices.

7) Research Assistant Aug'95 - Sep'97 Materials Science Research Center, Howard University, Washington, DC

* Manage Wide Band-gap Semiconductor Materials (AlN, GaN) Characterization task

* Built and maintenance homemade high energy (10keV) Cathode-luminescence ultra-vacuum (10-9 torr) system for the ultra-low temperature characterization of these materials

* Write and publish papers to the journal

8) Teaching Assistant Aug'91 - Aug'95 Physics Dept., Howard University, Washington, DC

* Teach regular Physics 101 class for Physics and Engineering Student

* Write questions for the exam

* Grade homework, quizzes, exam papers

* Submit final grade to the department

Computer Literacy

* JMP Statistical Software

* Microsoft Office

* C++ Programming (Learning Stage)

Summary of Educational Qualifications

* Ph.D. in Electrical Engineering, Arizona State University (Jan'98 to Sep'03), GPA 3.5/4.0

* M.S in Physics, Howard University (Aug'91 to Aug'96), GPA 3.58/4.0

* M.Sc. in Physics, University of Dhaka, Bangladesh (Feb'89 to Nov'91). Passed

* B.S in Physics, University of Dhaka, Bangladesh (Jun'83 to Feb'89), GPA 4.0/4.0

Honor & Award

* Awarded Lean Six Sigma Black Belt, Freescale Semiconductor Inc., December'10

* Awarded Lean Six Sigma Green Belt, Freescale Semiconductor Inc., July'09

* Awarded WriteON, ON Semiconductor, May'01.

* Awarded Silver Quill, Motorola Patent Department, Motorola Inc., October'99.

* Awarded Silver Quill, Motorola Patent Department, Motorola Inc., July'98.

* Awarded Scholarship in Dhaka University for Bachelor of Science degree in 1989.

Patents & Publications:

1. US Patent 7,709,864, High-efficiency Schottky rectifier and method of manufacturing same, May'10

2. US Patent 7,847,315, High efficiency rectifier, December'10

3. SPIE (The International Society for Optical Engineering) Proceeding, 3881, September'99.

4. Journal of Applied Physics Letters, Vol.72, No.12, p. 1501-1503, 23 March 1998.

5. SPIE (The International Society for Optical Engineering) Proc, 2877, 42-45, Oct'96, Invited Paper.

6. MRS (Materials Research Society) Proceeding, 449, p.119, December, 1996.

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