Siddhartha Chhabra

Email: abqot2@r.postjobfree.com

Ph: 919-***-****

Education August 2006 November 2010: PhD, Computer Engineering, Electrical and Computer

Engineering Department, North Carolina State University. (GPA: 4.0/4.0)

August 2003 June 2005: Master of Technology, Indian Institute of Information

Technology, Bangalore, India (GPA: 3.76/4)

August 1999 July 2003: Bachelor of Technology, G.G.S.I.P. University, Delhi, India

(CGPA: 3.8/4.0)

December 2010 Present: Research Scientist, Intel Labs

Work

Experience December 2006 November 2010: Research Assistant, North Carolina State University.

Member of ARPERS

May 2009 August 2009: Graduate Research Intern, Intel Labs (CTG-CSR), Oregon.

Worked on designing and prototyping a hardware protocol for secure communication

between Secure processor and a Secure co-processor

May 2008 August 2008: Graduate Research Intern, Intel Labs (CTG-STL-PSL), Oregon.

Worked on designing and prototyping Key provisioning infrastructure for a future Secure

Processor

August 2006 December 2006: Teaching Assistant, North Carolina State University

January 2005 August 2006: Software Engineer: Intel Corporation, Bangalore, India.

Worked with the Graphics Core engineering team.

Teaching Assistant for a course on Computer Architecture at IIIT, Bangalore, June 2004

November 2004

College intern at Tata Consultancy Services, India, September 2002 to November 2002

Publications Architecture support for Security

Siddhartha Chhabra and Yan Solihin. i-NVMM: A Secure Non-volatile Main Memory

System with Incremental Encryption, International Symposium on Computer

Architecture, (ISCA), June 2011

Siddhartha Chhabra and Yan Solihin. SecureME: A Hardware-Software Approach to

Full System Security, International Conference on Supercomputing, (ICS), May-June

2011

Siddhartha Chhabra and Yan Solihin. Green Secure Processors: Towards Power-

Efficient Secure Processor Design, Transactions of Computational Science, (TCS),

Special Issue on Security, 2010

Siddhartha Chhabra, Yan Solihin, Reshma Lal and Matthew Hoekstra. An Analysis Of

Secure Processor Architectures, Transactions of Computational Science, (TCS),

2010

Siddhartha Chhabra and Yan Solihin. Defining Anomalous Behavior for Phase

Change Memory, W orkshop on the Use of Emerging Storage and Memory

Technologies (WEST 2010) Held in conjunction with the 2010 International Symposium

on High-Performance Computer Architecture (HPCA), January 2010.

Siddhartha Chhabra and Yan Solihin. SHIELDSTRAP: Making Secure Processors

Truly Secure, International Conference on Computer Design (ICCD), October, 2009.

Siddhartha Chhabra and Yan Solihin. sProcVisor: A Hardware-Software Approach to

Full System Security, W orkshop on the Interaction between Operating Systems and

Computer Architecture (WIOSCA 2009) Held in conjunction with the 2009 International

Symposium on Computer Architecture (ISCA), June 2009

Siddhartha Chhabra and Yan Solihin. SHIELDSTRAP: A Secure Bootstrap

Architecture, W orkshop on the Interaction between Operating Systems and Computer

Architecture (WIOSCA 2009) Held in conjunction with the 2009 International

Symposium on Computer Architecture (ISCA), June 2009

Siddhartha Chhabra, Brian Rogers, Yan Solihin and Milos Prvulovic. Making Secure

Processors OS- and Performance-Friendly, ACM Transactions on Architecture and

Code Optimization (TACO), February 2009

Brian Rogers, Chenyu Yan, Siddhartha Chhabra, Milos Prvulovic and Yan Solihin.

Single Level Integrity and Confidentiality Protection for Distributed Shared

Memory Multiprocessors, to appear in Proc. of the 14th International Symposium on

High Performance Computer Architecture (HPCA), February 2008.

Brian Rogers, Siddhartha Chhabra, Yan Solihin and Milos Prvulovic. Using Address

Independent Seed Encryption and Bonsai Merkle Trees to Make Secure

Processors OS and Performance Friendly, Proc. of the 40th Annual IEEE/ACM

Symposium on Microarchitecture (MICRO), December 2007

Others

Ubiquitous rescue operation at affordable cost through location aware SMS

National Conference on Communications (NCC) -2005

Automatic Toll collection through affordable SMS: Accepted at ICCC 2005

Invention

Method and Apparatus of Super-scaling Crypto-Protection over computer DRAM: Approved

Disclosures for filing

A Low-Overhead Cryptographic Method and Apparatus for providing Memory confidentiality,

Integrity and replay protection: Approved for filing

SHIELDSTRAP: A Secure bootstrap architecture: Pending

I-NVMM: A secure Non-volatile Main Memory system with incremental encryption: Pending

Skills

Processor Simulators: SESC, Simplescalar, Simics, GEMS

Languages : Expert: C, C++, Assembly Language. Intermediate: VC++, C#,

(.NET), Java, Visual Basic, SQL, XAML,

Libraries: C/C++ Libraries :- Packet Capturing Library (libpcap) under

Linux, POSIX thread library (pthread) under Linux.

Databases: MS Access, SQL Server 2000

Web Technologies : HTML, Java Servlets and server pages

Other technologies: XML using JAXP, SVG, JFree,XAML

Platforms Linux, Windows.(XP, Longhorn)

Selected 1. Exceeding Data Flow Limit using Value Prediction: Implemented a spectrum of value

Projects predictors (last value, stride and context based) and integrated them in the processor

pipeline. Studied the various alternatives for recovering from mis-speculations: Re-injecting

dependents from the Active List (ROB) or Issue Queue (IQ) and complete squash of

mispredicted dependents. (Simplescalar)

2. Prefetch banks: Using a cache bank as a prefetch buffer: Implemented NUCA, and

partitioned the last level cache between prefetches and demand fetches. Studied the

performance for a stride and markov prefetcher. (SESC)

3. Multiprocessor Projects: RegionScout: A Technique to reduce the number of tag lookups

due to a snooping coherence protocol. Acacio s Upgrade predictor: A Technique to

speedup Upgrade misses by sending invalidations to predicted sharers without referring

the directory. (SIMICS/GEMS)

4. Implementing a trace based cache simulator and studying various cache

replacement policies (Language: C)

5. Implementing various branch predictors (gselect, Two level, and hybrid, Language:

C)

6. Implementing a C to S3 (A simplified instruction set) compiler, Register allocation,

dead code elimination and Iterative Modulo Scheduling (Language: C)

7. Implementing a Superscalar pipeline simulator: Implemented a simulator for an out-of-

order superscalar processor based on Tomasulo s algorithm that fetches and executes N

instructions per cycle. Also modeled the instruction cache with a next line prefetcher.

(Language: C).

8. Implementing and parallelizing programs for a shared memory parallel machine

using OpenMP.

9. Implementing MSI protocol for maintaining cache coherence for a multiprocessor

(SESC)

10. Implementing user level thread library (Language: C)

11. Implementing a lock library (Language: C)

12. Implementing a preemptive thread scheduler (Language: C)

13. Conducting buffer overflow attacks to change program behavior (Language: C)

14. Implementing Distributed mutual exclusion algorithm (Language: C)

Relevant

Computer Design and Technology (A+)

Courses

Parallel Computer Architecture (A+)

Operating Systems (A)

Computer security (A+)

Advanced Microarchitecture (A+)

Memory Systems (A+)

Advanced Parallel Architecture (A+)

Code Generation and Optimization (A+)

References

Available on Request

Contact this candidate