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Resume:

Accurate Pre-layout Estimation of Standard Cell

Characteristics

Hiroaki Yoshida Kaushik De Vamsi Boppana

Zenasis Technologies, Inc. Zenasis Technologies, Inc. Zenasis Technologies, Inc.

Campbell, CA 95008-6900 Campbell, CA 95008-6900 Campbell, CA 95008-6900

*******@*******.*** *******@*******.*** *****@*******.***

ABSTRACT

Less Accurate

Approach 1

Faster

pre-layout

netlist

With the advent of deep-submicron technologies, it has become es- Cell

Design

Characterizer

timing/

Optimizer

sential to model the impact of physical/layout e ects up front in power etc.

all design ows [1]. The e ect of layout parasitics is consider-

Approach 2

able even at the intra-cell level in standard cells. Hence, it has pre-layout

pre-layout

become critically important for any transistor-level optimization to netlist

netlist Cell Layout

Design

consider the e ect of these layout parasitics as an integral part of

Characterizer

timing/ Estimator

Optimizer estimated

More Accurate

power etc. netlist

the optimization process. However, since it is not computationally

Approach 3

feasible for the actual layout to be a part of any such optimization

pre-layout pre-layout

procedures, we propose a technique that estimates cell layout char-

Slower

Layout

netlist netlist

Cell

Design

post-layout Synthesizer

Characterizer

timing/

Optimizer

acteristics without actually performing the layout and subsequent power etc. netlist

extraction steps. We demonstrate in this work that it is indeed fea-

sible to estimate the layout e ects to get timing characteristics that

Figure 1: Transistor-level optimization approaches.

are on average within about 1.5% of post-layout timing and that

the technique is thousands of times faster than the actual creation

of layout.

Categories and Subject Descriptors increasingly used in the creation of high-performance libraries and

B.7.2 [Hardware]: Integrated Circuits Design Aids are equipped to handle a variety of manufacturing, design and cost

considerations used in the creation of libraries [10].

General Terms Traditionally, transistor-level optimization techniques such as [2]

[11], have not attempted to account for the impact of layout para-

Algorithms, Measurement, Performance, Design sitics, which has become increasingly important at the 130nm and

at the 90nm process nodes [1]. The e ect of these layout parasitics

Keywords has become extremely important, even for circuits with a small

number ( 10) of transistors, rendering any optimization without

Standard cell, cell characterization, transistor-level optimization

considering these e ects to be impractical. In addition, reduced or-

der device models such as switch-level (RC) models of transistors

1. INTRODUCTION

are becoming increasingly incapable of modeling deep submicron

Design optimization at the transistor-level is well-known and

e ects. This leaves detailed simulation, often at the BSIM3/4 level

has been used successfully to achieve signi cant performance ben-

[12], or using detailed models built using simulation at that level,

e ts above and beyond gate-level design optimization. The ap-

as the only reliable option for obtaining accurate circuit timing.

proaches range from transformations such as sizing [2][3], all the

Hence, it has become critically important for any transistor-level

way to macro-cell based design methodologies [4]. More recently,

optimization to consider the e ect of these layout parasitics as an

transistor-level optimization techniques targeting a standard cell

integral part of the optimization process. In other words, out of the

based design ow have also been proposed [5]-[7]. These opti-

design optimization approaches outlined in Figure 1, Approach 1

mization techniques take advantage of the recent progress in auto-

is not practical for deep submicron geometries. On the other hand,

mated cell-layout solutions [8][9]. Such solutions are now being

it is also not computationally feasible to wait for the actual layout

to be a part of any such optimization procedures, as suggested by

Approach 3 in Figure 1. Hence, we propose a technique that pro-

vides an accurate estimate of cell layout characteristics without ac-

Permission to make digital or hard copies of all or part of this work for

tually performing the layout and subsequent extraction steps. This

personal or classroom use is granted without fee provided that copies are

not made or distributed for pro t or commercial advantage and that copies is Approach 2 outlined in Figure 1. We demonstrate in this work

that it is indeed feasible to estimate the layout e ects to get timing

bear this notice and the full citation on the rst page. To copy otherwise, to

republish, to post on servers or to redistribute to lists, requires prior speci c characteristics that are on average within about 1.5% of post-layout

permission and/or a fee.

timing and the technique is thousands of times faster than the actual

DAC 04, June 7 11, 2004, San Diego, California, USA.

creation of layout.

The rest of the paper is organized as follows. Section 2 intro- A Maximal Transistor Series (MTS) is a maximal set of series-

duces the layout model, circuit model and problem de nition. Sec- connected transistors. In a physical layout, an MTS is typically

tions 3 and 4 describe the proposed statistical and constructive esti- implemented as transistors that are connected to each other by dif-

mation techniques respectively and Section 5 presents experimental fusion. An intra-MTS net is a net that connects two transistors in

results on two industrial processes at the 130nm and 90nm process an MTS and an inter-MTS net is a net that connects transistors in

di erent MTSes. Figure 4 shows an example of an MTS and its

nodes. Conclusions are drawn in Section 6.

physical implementation. MTS identi cation is an essential step in

building a high-quality estimator.

2. PRELIMINARIES

In this section, we rst present our models of cells, layouts and Inter-MTS Net

circuits. We then describe several notions used throughout this pa- B A C D F E

X Intra-MTS Net

per. Finally, the problem addressed in this paper is formulated.

A cell refers to a typical standard cell. Figure 2 illustrates our X

A C

cell layout model. A cell is of a single-height style, i.e., P-type

and N-type transistors are placed in di usion regions as shown. No F

B D

transistor stacking is allowed. The region between the two di usion

MTS

regions is called as the di usion gap region. Maximum di usion Y

heights are either xed or exible, depending on the layout style.

Transistors are connected by using either wires or di usion. Figure 4: Maximal Transistor Series (MTS) and its physical

implementation.

Power Rail

Cell characterization refers to the process of determining vari-

Minimum Poly-to-Poly Spacing

ous characteristics (such as timing, power, input capacitances) of

Transistor Region Height

the cell. This process is used to create views/models of the cell that

P-type

Diffusion

Diffusion Gap Height

are used in various steps of the design ow. Of particular interest

Region

in this paper is the aspect of cell timing characterization. It refers to

the process of creating models such as the non-linear delay model

Minimum Poly-to-Contact Spacing

[13] based on detailed SPICE simulation of the transistor-level cir-

cuit representation of the cell. Cell timing represents four di er-

N-type

Diffusion Contact Width ent timing characteristics, i.e., cell rise, cell fall, transition rise and

Region

transition fall, for a pre-de ned set of output loads and input slews,

on every signal-carrying input-to-output path in the circuit.

Ground Rail

Without loss of generality, timing T (c) of a cell c can be de ned

as a delay or slew of an arc of the cell for a given output load and

Figure 2: Our layout model.

input slew. Pre-layout timing T pre (c), estimated timing T est (c) and

post-layout timing T post (c) are the timing values that are obtained

Figure 3 shows our circuit models. A pre-layout netlist is a set by characterizing a pre-layout netlist, estimated netlist and post-

of transistors and nets that connect transistors. Each transistor in layout netlist, respectively.

a pre-layout netlist has its length and width. An estimated netlist The problem addressed in this paper can be formulated as fol-

is de ned as a pre-layout netlist with the following modi cations. lows: Given a cell c and its pre-layout netlist, nd an estimated

Each transistor has the areas and perimeters of its drain and source timing such that the absolute di erence of the estimated timing and

di usion regions in addition to its width and length. Each net has post-layout timing:

an associated grounded capacitance. An estimated netlist is func-

D(c) = T est (c) T post (c) (1)

tionally identical to the corresponding pre-layout netlist but can be

structurally di erent due to transistor folding, i.e., a wide transistor

is minimized.

in a pre-layout netlist may be split into smaller parallel-connected

transistors in the estimated netlist.

3. STATISTICAL ESTIMATOR

M1 n1 a vdd vdd p W=2.0u L=0.13u

One can estimate post-layout timing from pre-layout timing based

+ AD=0.36e-12 AS=0.36e-12

on statistical analysis of di erences between pre-layout and post-

+ PD=4.36e-6 PS=4.36e-6

layout timing. The statistical estimator estimates the post-layout

M1 n1 a vdd vdd p W=2.0u L=0.13u C1 n1 vss 1.2f

timing of a cell by multiplying pre-layout timing by a predeter-

mined scale factor S .

Folded Transistors

T est (c) = S T pre (c) (2)

S is speci c to each technology and cell architecture, and is deter-

mined based on a small representative set of cells that are actually

laid out and characterized with respect to timing. More speci cally,

the scale factor is calculated as follows:

Wiring Capacitances

S= (T post (c)/T pre (c)) (3)

(b) Estimated netlist.

(a) Pre-layout netlist.

C c C

Figure 3: SPICE-level and schematic-level descriptions of our

where C is a representative set of cells.

circuit models.

with the di usion is an intra-MTS net or an inter-MTS net.

The advantage of this estimator is that it is applicable to any tech-

nology and cell architecture because it is formulated in a technology- S pp /2 if n is intra-MTS net

w= (10)

independent manner. On the other hand, the disadvantage is its in- Wc /2 + S pc if n is inter-MTS net

accuracy mainly due to the lack of consideration of the variation of

where S pp is the minimum poly-to-poly spacing, Wc is the contact

layout characteristics. The experimental results in Section 5 show

width and S pc is the minimum poly-to-contact spacing. These are

that this approach is not accurate enough. In the next section, we ll

given as design rules as shown in Figure 2. Figure 5 illustrates

introduce the constructive estimator that takes such variations into

the estimation of di usion area and perimeter. It is important to

account.

note the role of an MTS in this computation. It is the MTS that

typically controls di usion sharing and hence controls the di usion

4. CONSTRUCTIVE ESTIMATOR

parasitics. This is the key to getting an accurate estimate of the

The central problem with the statistical estimator is that it cannot di usion parasitics.

accurately capture the variation of layout characteristics present in

di erent standard cells even from within the same standard cell li-

brary. In this section, we introduce the constructive estimator that

takes such variations into account. The constructive estimator con-

Diffusion Region

Transistor Width

Diffusion Region

Transistor Width

structs an estimated netlist by applying the following transforma-

tions to a pre-layout netlist: a) folding each transistor, b) assigning

di usion areas and perimeters to each transistor, and c) adding a

wiring capacitance to each net. Then estimated timing is obtained

by characterizing the estimated netlist. These transformations are

described in detail in the following subsections. Contact Width+

Minimum Poly-to-Poly Spacing

2*(Minimum Poly-to-Contact Spacing)

4.1 Transistor Folding

(a) Intra-MTS (b) Inter-MTS

Since the height of a cell is xed, a wide transistor in a pre-layout

Figure 5: Estimation of di usion area and perimeter.

netlist is divided into smaller transistors to meet the cell height.

Folded transistors are connected in parallel to preserve the original

Note that this transformation must be done after transistor fold-

functionality as illustrated in Figure 3.

ing because the widths of transistors may be di erent before and

The folded transistor width W f and the number of the folded

after transistor folding. It should also be noted that di usion area

transistors N f are calculated as follows:

and perimeter modeling should be made in conjunction with the

W f (t) = W (t)/N f (t) (4) transistor models of the target technology.

N f (t) = W (t)/W f max (t) (5)

4.3 Wiring Capacitance

R(Htrans Hgap ) if t is P-type

W f max (t) = (6) This transformation adds a wiring capacitance to each net in

(1 R)(Htrans Hgap ) if t is N-type

a pre-layout netlist. Intra-MTS nets are not considered because

they are typically implemented in di usion. Similar to di usion

where W (t) is the width of a given transistor t, x denotes the

area/perimeter estimation, this transformation must be done after

smallest integer greater than or equal to x, R is the ratio of heights

of the P and N di usions, Htrans is the height of a transistor region transistor folding.

and Hgap is the height of a di usion gap region as shown in Figure The capacitance C (n) of a net n is estimated by the following

2. formula:

Our model allows two transistor folding styles, a xed P/N ratio

C (n) = M T S (t) + M T S (t) + (11)

style and an adaptive P/N ratio style. In the xed P/N ratio style,

t T DS (n) t TG (n)

R is speci c to a given technology and cell architecture. In the

where, and are constants, T DS (n) is a set of transistors whose

adaptive P/N ratio style, R is speci c to a cell and is determined

drain or source is connected to a net n, TG(n) is a set of transistors

such that the width of the cell is minimized:

whose gate is connected to a net n and MT S (t) is an MTS that

R= W (t) W (t) (7) includes a transistor t. According to our experiments presented in

t P(c) t P(c) N (c) Section 5, the above formula gives an excellent correlation to actual

wiring capacitances. Again, it is important to note the importance

where P(c) is a set of P-type transistors in a cell c and N (c) is a set

of MTS in obtaining an accurate estimate of wiring capacitance.

of N-type transistors.

It is the MTS connectivity that typically dictates the length of the

4.2 Diffusion Area and Perimeter wire and hence the capacitance of the wire.

Formula (11) requires three constants, and to be determined

Given the width w and height h of the di usion region of a tran-

sistor, the di usion area A and perimeter P are calculated as fol- in advance. These constants are determined by multiple regression

analyses based on a small representative set of cells that are actually

lows:

laid out. This calibration process has to be done only once for a

A = wh, P = 2w + 2h (8) given technology and cell architecture.

The height of a di usion region is estimated as the width of the

5. EXPERIMENTAL RESULTS

associated transistor t:

The proposed technique has been implemented within the frame-

h = W (t) (9)

work of a standard cell characterization ow. Given a pre-layout

The width of a di usion region is estimated by using one of the fol- netlist, cell timing is generated based on both statistical and con-

lowing formulas depending on whether the net n that is associated structive estimations and compared with post-layout timing. As

Table 1: Quality of proposed estimation techniques for two industrial standard cell libraries.

No Estimation Statistical Estimator Constructive Estimator

Feature Size

Avg. Abs. Di . Std. Dev. Avg. Abs. Di . Std. Dev. Avg. Abs. Di . Std. Dev.

#Cells #Wires

[nm]

[%] [%] [%] [%] [%] [%]

130 57 276 8.85 4.08 3.60 2.76 1.55 1.79

90 53 221 8.81 4.80 4.10 3.35 1.52 1.40

6. CONCLUSIONS

Estimated capacitance [fF]

We have demonstrated that it is feasible to estimate timing char-

acteristics of transistor-level circuits in a standard-cell design frame-

5 work to on average within about 1.5% of post-layout timing based

on a fast and accurate constructive estimation technique. This tech-

4 3

nique solves a critical problem a ecting transistor-level optimiza-

tion techniques at deep submicron geometries. It has been imple-

mented in an industrial software system and has been successfully

used at today s leading edge process nodes.

0 0

0 1234567 8 0 1 2 3 4 5 6

Extracted capacitance [fF]

7. REFERENCES

(a) 130nm technology (b) 90nm technology [1] International Technology Roadmap for Semiconductors 2002

Update, Semiconductor Industry Association, 2002.

Figure 6: Extracted versus estimated capacitances.

[2] J. P. Fishburn and A. E. Dunlop, TILOS: A posynomial

programming approach to transistor sizing, in Proc. of IEEE

discussed in Section 4, for the statistical technique, cell timing

International Conference on Computer-Aided Design, pp.

is generated based on calibrating simulation results from a pre-

326 328, Nov. 1985.

layout netlist. For the constructive technique, the estimated netlist

[3] A. Conn et al., Gradient-Based Optimization of Custom

(with transistor folding, di usion area/perimeter and wiring capac-

Circuits Using a Static-Timing Formulation, in Proc. of

itances) is simulated.

ACM/IEEE Design Automation Conference, pp. 452 459,

We conducted experiments on two di erent state-of-the-art stan-

Jun. 1999.

dard cell libraries implemented in 130nm and 90nm technologies.

[4] J. L. Burns and J. A. Feldman, C5M A Control- Logic

These libraries were chosen at di erent process nodes and from

Layout Synthesis System for High-Performance

di erent vendors in order to measure the e ectiveness of the tech-

Microprocessors, IEEE Trans. on Computer-Aided Design,

niques across varying layout styles and design rules. The cells vary

vol. 17, no. 1, pp. 14 23, Jan. 1998.

from simple cells such as an inverter to complex cells that consist of

30 unfolded transistors. The simulator used in these experiments [5] R. Panda et al., Migration: A new technique to improve

synthesized designs through incremental customization, in

was HSPICE[14].

Proc. of ACM/IEEE Design Automation Conference, pp.

First, we present results that demonstrate the e ectiveness of the

388 391, Nov. 1998.

constructive technique on estimating wiring capacitances. Wiring

[6] M. Cote and P. Hurat, Faster and Lower Power Cell-Based

capacitances critically determine the quality of the constructive es-

timator due to their increased e ects at the deep submicron geome- Designs with Transistor-Level Cell Sizing, in Closing the

Gap Between ASIC & Custom, pp. 225 240, Kluwer

tries. Figure 6 shows scatter plots that compare extracted and es-

Academic Publishers, 2002.

timated wiring capacitances for the cells in the 130nm and 90nm

[7] D. Bhattacharya and V. Boppana, Design Optimization with

technologies, respectively. The extracted capacitance values are

Automated Flex-Cell Creation, in Closing the Gap Between

calculated from lumped C extracted netlists. The three constants

ASIC & Custom, pp. 241 268, Kluwer Academic Publishers,, and in Formula (11) for these technologies are calculated by

multiple regression analyses. This data shows the excellent corre- 2002.

lation achieved by our wiring capacitance estimation technique. [8] M. Guruswamy et al., CELLERITY: A Fully Automatic

Finally, Table 1 demonstrates the e ectiveness of the estimators Layout Synthesis System for Standard Cell Libraries, in

Proc. of ACM/IEEE Design Automation Conference, pp.

on overall cell timing for the two standard cell libraries under con-

sideration. All four kinds of cell delays (cell rise, cell fall, transition 327 332, Jun. 1997.

rise, transition fall) are measured in this experiment. Columns 1, 2 [9] abraCAD Documentation, Synopsys, Inc., 2003.

and 3 show the feature size of the library, the number of cells used [10] C. Bittlestone et al., Architecting ASIC Libraries and Flows

in this experiment and the number of wires whose capacitances are in Nanometer Era, in Proc. of ACM/IEEE Design

estimated in this experiment. The rest of the columns compare Automation Conference, pp. 776 781, Jun. 2003.

the quality of the cell timing for each of the proposed techniques. [11] S. S. Sapatnekar et al., An Exact Solution to the Transistor

For example, for the 90nm technology library, if no estimation was Sizing Problem for CMOS Circuits Using Convex

used, the average of the absolute di erences in timing is 8.85% and Optimization, IEEE Trans. on Computer-Aided Design, vol.

a standard deviation of 4.08%. The statistical approach produces 12, no. 11, pp. 1621 1634, Nov. 1993.

an average absolute di erence of 4.10% and a standard deviation

[12] W. Liu et al., BSIM3v3.2 MOSFET Model Users Manual,

of 3.35%. And nally, the best results are obtained by the construc-

University of California, Berkeley, 1998.

tive estimator, with an average absolute di erence of 1.52% and a

[13] Library Compiler User Guide: Modeling Timing and Power

standard deviation of 1.40%. It is worth noting that the runtimes of

Technology Libraries, Synopsys, Inc., 2003.

the constructive estimators are very small, with typical overheads

[14] HSPICE Data Sheet, Synopsys, Inc., 2003.

being less than 0.1% of typical SPICE simulation times.

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