Electrical Engineering
Resume:
CURRICULUM VITA
Zainalabedin
Navabi
Electrical and Computer Engineering
Worcester Polytechnic Institute
Worcester,
Massachusetts 10609
Email: abql2p@r.postjobfree.com
(Office);
(Res); +1-617-***-**** (Fax)
PERSONAL:
Married, and two
children
EDUCATION:
1978 1981:
Ph.D. in
Electrical Engineering, University of Arizona, Tucson, Arizona 85721
Research: VLSI
Design Automation Using A Hardware Programming Language
Minor: Computer
Science
1975 1978:
M.S. in
Electrical Engineering, University of Arizona, Tucson, Arizona 85721
Research:
Digital System Simulation at the Register Transfer LevelMinor: Computer Science
1971 1975:
B.S. in Electrical
Engineering, University of Texas, Austin, Texas 78712
Graduated With HIGHEST HONORS with Grade Point Average of 3.9
SPECIALIZATION:
Specialized in
Hardware Description Languages, Digital System Simulation, VLSI Design
Automation, Modeling, Digital System Test, Hardware Generation, and Silicon
Compilation. Have developed or directed development of programs for Register
Transfer Level simulation, PAL fuse layout generator, Minimum complex gate
implementation of digital circuits, behavioral and component synthesis, back
annotation and extraction programs, HDL based tools, data flow and behavioral
HDL based synthesis tools, Test generation programs, and several testable
design generation tools.
PROFESSIONAL
AFFILIATIONS:
Institute of
Electrical and Electronic Engineers (IEEE)
IEEE Computer
Society
American Society
of Engineering Education (ASEE)
European
Association for Microprocessing and Microprogramming (EUROMICRO)
Association of
Computing Machinery (ACM)
HONORS:
Graduated with
HIGHEST HONORS, University of Texas at Austin, May '75.
Motorola Merit
Scholarship Award, October 1981.
WORK EXPERIENCE:
8/92
Present:
Professor,
Electrical and Computer Engineering Department, University of Tehran, Tehran Iran. Responsible for Computer Engineering group of the ECE Department.
Teaching graduate courses in modeling, digital circuit design, and testing.
Responsible for developing new graduate courses on testability and fault
tolerance. Courses taught include undergraduate computer engineering, VLSI
design courses, digital circuit test and testability, and graduate digital
system design with hardware description languages. Present research includes
study of modeling strategies of hardware for design, synthesis and test.
8/92-present:
Adjunct Professor,
Electrical and Computer Engineering Department, Northeastern University, Boston, Massachusetts, USA. Responsible for teaching HDL and digital systems courses and
research in simulation algorithms. Performs summer NTU courses, as well as
several short non- credit HDL courses. Conducts research on HDL modeling for
simulation and test.
8/91
8/92:
Associate
Professor, Electrical and Computer Engineering Department, Northeastern
University, Boston, Massachusetts, USA. Holding the ITC endowment Chair.
Teaching Computer and Digital System, and VLSI Courses. Responsible for
developing a new HDL based graduate course, and for bringing extensive use of
CAD tools in the basic logic course. Courses taught include undergraduate
computer engineering, VLSI design courses; and graduate digital system design
with hardware description languages. Research in Hardware Description
Languages, timing analysis, simulation, modeling, hardware synthesis, analysis
of behavior of hardware, back annotation, and Silicon Compilation.
8/87
8/91:
Assistant
Professor, Electrical and Computer Engineering Department, Northeastern
University, Boston, Massachusetts, USA. Teaching Computer and Digital System,
and VLSI Courses. Responsible for bringing extensive use of CAD tools in the
basic logic course. Courses taught include undergraduate computer engineering,
VLSI design courses; and graduate digital system design with hardware
description languages. Research in Hardware Description Languages, timing
analysis, simulation, hardware synthesis, analysis of behavior of hardware, and
Silicon Compilation.
8/86
8/87:
Visiting
Assistant Professor, Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ USA. Teaching Computer and Digital System Courses, including
circuit theory, logic design and microprocessor, and digital circuit design.
Research in VLSI Design Automation and Hardware description Languages.
8/83
8/86:
Assistant
Professor, Electrical Engineering Department, Sharif University of Technology, Iran. Teaching circuit theory, microprocessor, logic design, and computer organization courses.
Research in Hardware Description Languages and Hardware Compilation.
Development of the Computer Engineering Curriculum and Graduate Study Program
for the Computer and Electrical Engineering Department. Developed software for
silicon compilation from AHPL.
1/82
6/83:
Visiting
Assistant Professor, and Research Associate in the Electrical and Computer
Engineering, University of Arizona, USA. Taught basic Electrical Engineering
and CAD courses. Developed and taught a graduate course on the computer aided
design of digital circuits. Research in Hardware Description Languages and
VLSI Design Automation.
6/79
12/81:
Graduate
Research Associate, University of Arizona. Major research in Automation of
VLSI Design.
9/78
9/79:
Graduate
Teaching Associate, University of Arizona. Assisted is teaching digital system
courses. System Programmer, Interactive Graphic Engineering Laboratory,
Aerospace and Mechanical Engineering Department, University of Arizona. Duties included development of a digitizing program for digitizing two dimensional
structures for finite element analysis, and Interface to Eclipse computer.
EXPERTISE:
Experienced in
interface design and computer graphics. Thorough understanding of digital
system design, microprocessors, compiler design and language implementation,
compiler compilers, data structures, operating systems, field
programmable devices and related CAD tools, and custom and semi custom
VLSI chip design and CAD tools. Have worked on Electrical and Computer
Engineering curriculum of several universities and have developed graduate
programs in this field.
JOURNAL
PUBLICATIONS:
[1]
H.
A. Kamel and Z. Navabi, "Digitizing for Computer Aided Finite
Element Model Generation Part 1. The Generation Program," Transactions
of the ASME, July 1980.
[2]
Z.
Navabi and H. A. Kamel, "Digitizing for Computer Aided Finite
Element Model Generation Part 2. Use of Digitizing in Mesh
Generation," Transactions of the ASME, July 1980.
[3]
F.
J. Hill, R. Swanson, Z. Navabi and M. Masud "Structure Specification with
a Procedural Hardware Description Language," IEEE Transactions on
Computers, February 1981, pp. 157 161.
[4]
F.
J. Hill, Z. Navabi, C. H. Chiang, D. P. Chen, and M. Masud "Hardware
Compilation of AHPL Descriptions to an SLA Target," IEEE Transactions
on Computer Aided Design, June 1984.
[5]
Z.
Navabi, "Generating Gate Level Two Phase Dynamic MOS Logic From
AHPL," EUROMICRO Journal on Microprocessing and Micrprogramming,
September/October 1985.
[6]
Z.
Navabi and K. Doroudi, "Compiling an RT Level Hardware Description
Language into Layout of NMOS Cells," EUROMICRO Journal on
Microprocessing and Microprogramming, December 1986, Volume 18, Numbers 1 5.
[7]
Z.
Navabi and Kia Doroudi, "HDL Front End For a Cell Based Silicon
Compiler," International Journal of Computer Simulation," 1991 1992,
Ablex Publishing Corporation, Norwood, New Jersey.
[8]
Z.
Navabi, "Compiling Gate RC Models Into a Top Level Simulation Model for Rough
Timing Analysis of VLSI Circuits," Journal of Microprocessors and
Microsystems, Butterworth Heinemann Publishing, July August 1991.
[9]
Z.
Navabi, "A High Level Language For Design and Modeling of Hardware," Journal
of Systems and Software, Elsevier Publishing Company, December 1991 or
Early 1992.
[10] Z. Navabi and M.
Massoumi, "Investigating Back Annotation of High Level
Descriptions," The International Journal of Simulation, Society of
Computer Simulation, November 1991.
[11] Z. Navabi,
"A Description Style for Automatic Hardware Synthesis," Journal
of Computer Applications in Technology.
[12] Z. Navabi and
John Spillane, "Synthesis of VLSI Circuits From Behavioral
Descriptions," Microelectronics Journal, Elsevier Advanced
Technology Publishing, December 1991.
[13] Z. Navabi and
Mehran Massoumi, "Design and Description of Hardware Using a Standard
Hardware Language," Microelectronics Journal, Elsevier Advanced Technology
Publishing
[14] Z. Navabi and
Zahra Razavi, A Transistor Level Link for VHDL Simulation of VLSI Circuits, Simulation
Journal, September 1995.
[15] Z. Navabi
with Bijan Alizadeh and Mohammad Reza Kakoee, "A New High Level Model
Based on Integer Equations to Check CTL Properties in VHDL Environment",
WSEAS Transactions on Circuits, Issue 1, Volume 2, January 2003
[16] Z. Navabi
with Maghsoud Abbaspour, "Architecture Modeling for retargeting a
disassembler Binary Tool", WSEAS Transactions on Computers, Issue 3,
Volume 2, July 2003
[17] Z. Navabi
with M. H. Tehranipour, M. Nourani, S. M. Fakhraie, and M. R. Movahedin, "Embedded
Test for Processor and Memory Cores in
System-on-Chips," to appear in International Journal of Science and Technology
(Scientia Iranica), October 2003.
[18] Zainalabedin Navabi with M.H. Tehranipour, S.M. Fakhraei
and M.R. Movahedin, "A Low-Cost At-Speed BIST Architecture for Embedded
Processor and SRAM Cores", Journal of Electronic Testing: Theory and
Applications 20, 155-168, 2004
[19] Zainalabedin Navabi with Farzin Karimi, Waleed M. Meleis
and Fabrizio Lombardi, " Using Data Compression in Automatic Test
Equipment for System-on-Chip Testing", IEEE Transaction on Instrumentation
and Measurement, Vol. 53, NO. 2, April 2004
[20]
Zainalabedin Navabi with Mehran Nadjarbashi and Shahrzad Mirkhani,
A Method of Structural Equivalence Fault Collapsing for HDL Implementation,
Integration, the VLSI Journal, Submitted.
[21] Zainalabedin Navabi with Shahrzad Mirkhani, Meisam Lavasani, and Fabrizio
Lombardi Using RT Level Component
Descriptions for Single Stuck-at Hierarchical Fault Simulation, Journal of
Electronic Testing, Kluwer Publishing, Submitted.
[22] Zainalabedin Navabi with Saeed Shamshiri and Hadi
Esmaeilzadeh, Instruction- Level Test Methodology for CPU Core Self-Testing,
ACM Transactions on Design Automation of Electronic Systems, Vol. 10, No. 4,
October 2005, pp. 673-689.
[23] Zainalabedin Navabi with Ehsan Atoofian, A Test
Approach for Look-Up Table Based FPGAs, Journal of Computer Science and
Technology, Kluwer Boston Inc., Vol. 21, NO. 1, pp. 141-146, January 2006.
[24] Zainalabedin Navabi with Sh. Sharifi, J. Jafari, M.
Hosseinabady and A. Afzali-Kusha, Scan-Based Structure with Reduced Static and
Dynamic Power Consumption, Journal of Low Power Electronics, Vol. 2, No.3, pp.
477-487, Dec. 2006.
[25] Zainalabedin Navabi with M. Hosseinabady and Pejman
Lotfi-Kamran, Low Test Application Time Resource Binding for Behavioral
Synthesis, ACM Transactions on Design Automation of Electronic Systems, Vol.
12, No. 2, Article 16, April 2007.
[26] Zainalabedin Navabi with Ali Shahabi, Nima Honarmand
and Hassan Sohofi, Degradable mesh-based on-chip networks using programmable
routing tables, IEICE Electronics Express, Vol. 4, No. 10, pp. 332-339, May
25, 2007.
[27] Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio
Lombardi, and Zainalabedin Navabi, "An RTL Datapath Test Generation Based
on Modular Arithmetic Equations," submitted to the IEE Proc. Computers
& Digital Techniques
[28] Mohammad Hosseinabady, Shervin Sharifi, Zainalabedin
Navabi, "Reducing Test Power, Time and Data Volume Using
Partially-Specified Test Vectors," submitted to the Integration VLSI
Journal, Elsevier Publishing.
[29] Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio
Lombardi, and Zainalabedin Navabi, Low Overhead DFT Using CDFG by Modifying
Controller, Computers & Digital Techniques, IET, Volume
1,, Page(s):322-333,
July 2007.
[30] Mohammad Hosseinabady, Shervin Sharifi, Fabrizio
Lombardi, Zainalabedin Navabi, A selective trigger scan architecture for VLSI
testing, IEEE Transaction on Computers, Volume
57,, Page(s):316
328, March 2008
[31] M. R. Jamali, M. Dehyadegari, A. Arami, C. Lucas, Z.
Navabi, Real-time Embedded Emotional Controller, Neural Computer &
Application, Springer, January 2008
[32] M. Saneei, A. Afzali-Kusha, Z. Navabi, A Low-Power
High Throughput Link Splitting Router for NoCs, Journal of Zhejiang
University-SCIENCE A, Vol. 9, No. 12, Page(s) 1708-1714, 2008
[33] N. Karimi, A. Alaghi, M. Sedghi, Z. Navabi, Online
Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch
Faults, Journal of Universal Computer Science, Vol. 14, No. 22, Dec. 2008
[34] M. Saneei, A. Afzali-Kusha, Z. Navabi, Sign Bit
Reduction Encoding For Low Power Applications, Journal of VLSI Signal
Processing Systems, Springer, Vol. 57, No. 3, Page(s) 321-329, September 2009
[35] M. R. Jamali, A. Arami, M. Dehyadegari, C. Lucas, Z.
Navabi, Emotion on FPGA: Model driven approach, Elsevier Publishing, Volume
36, Number 4, May 2009
[36] N. Mahani, P. Mokri, Z. Navabi, System Level
Hardware Design and Simulation with SystemAda, Ada Letters, A Publication of
SIGAda, the ACM Special Interest Group on Ada, Volume 29, Number 1, Page(s):
19-22, April 2009
[37] P. Lotfi-Kamran, A. Rahmani, M. Daneshtalab, A.
Afzali-Kusha, Z. Navabi, EDXY A Smart Congestion-Aware and Link Failure
Tolerant Routing Algorithm for Network-on-Chips, Journal of Systems
Architecture, ELSEVIER, Vol. 56, No. 7, Page(s) 256-264, July 2010
MAGAZINES:
[1]
"System Test: What, Why, and
How?" A D&T Roundtable for the IEEE Publication, Design and Test of
Computers; August 1990; with Jack Arabian, Robert Rolfe, Muary Smeyne, Harold
Carter, and Ernie Millham.
MANUALS and
WORKBOOKS:
[1]
Z. Navabi and F. J. Hill, "User
Manual for AHPL Simulator (HPSIM2) / AHPL Compiler (HPCOM)," Published by
Engineering Experiment Station, University of Arizona, December 1, 1988.
[2]
Z. Navabi and John Sutter, "User
Manual for OCT2HILO Program," Published by Massachusetts Microelectronics Center, Westboro MA, February 15 1991.
[3]
Z. Navabi, "Advanced VHDL for
Hardware Design and Modeling," Published by Okura and Company Ltd. Tokyo, Japan October 1993.
BOOKS:
[1]
Z. Navabi, "VHDL: Analysis and
Modeling of Digital System," McGraw Hill Company, N.Y., New York, 1993.
[2]
Z. Navabi, "VHDL: Analysis and
Modeling of Digital System," Second Edition. McGraw Hill Company, N.Y., New York, 1998.
[3]
Z. Navabi, "Verilog Digital System
Design," McGraw Hill Company, N.Y., New York, 1999, ISBN: 0-07-047164-0.
[4]
Z. Navabi, "Verilog Computer-Based Training Course", McGraw Hill Company, N.Y., New York, 2002, ISBN:
0-07-137473-6.
[5]
Z. Navabi, "Digital Design and
Implementation with Field Programmable Devices", Kluwer Academic Publishers, 2004, ISBN: 1-4020-8011-5.
[6]
Z. Navabi, "Verilog Digital System
Design", Second Edition.
McGraw Hill Company, N.Y., New York, 2006, ISBN: 0-07-144564-1.
[7]
Embedded Core Design with FPGAs";
August 1, 2006; McGraw Hill-Professional; ISBN: 007*******.
[8]
VHDL: Modular Design and Synthesis of
Cores and Systems, 3E; April 2007; McGraw Hill-Professional; ISBN:
978-0071475464.
[9]
Digital System Test and Testable
Design: Using HDL Models and Architectures; January 2011; Springer; ISBN:
978-1-4419-7547-8.
BOOK CHAPTERS:
[1]
Z. Navabi, Chapter 81, Hardware
Description in Verilog: An Overview, The VLSI Handbook, CRC IEEE PRESS, 2000,
ISBN: 0-8493-8593-8.
[2]
Z. Navabi, Section XIII, Design
Languages, Section Editor, The VLSI Handbook, Second Edition (Electrical
Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[3]
Z. Navabi, Chapter 85: Languages for
Design and Implementation of Hardware, The VLSI Handbook, Second Edition
(Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[4]
Shahrzad Mirkhani and Zainalabedin Navabi, Chapter 86, System Level
Design Languages, The VLSI Handbook, Second Edition (Electrical Engineering
Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[5]
Mahsan Rofouei and Zainalabedin Navabi,
Chapter 87, RT Level Hardware Description with VHDL, The VLSI Handbook, Second
Edition (Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[6]
Zainalabedin Navabi, Chapter 88,
Register Transfer Level Hardware Description with Verilog, The VLSI Handbook, Second
Edition (Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[7]
Shahrzad Mirkhani and Zainalabedin Navabi, Chapter 89,
Register-Transfer Level Hardware Description with SystemC, The VLSI Handbook, Second
Edition (Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[8]
Naghmeh Karimi and Zainalabedin Navabi,
Chapter 91 VHDL-AMS Hardware Description Language, The VLSI Handbook, Second
Edition (Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[9]
Hamid Shojaei and Zainalabedin Navabi,
Chapter 92, Verification Languages, The VLSI Handbook, Second Edition
(Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[10] Naghmeh Karimi and Zainalabedin Navabi 93 ASIC and
Custom IC Cell Information Representation, The VLSI Handbook, Second Edition
(Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[11] Shahrzad Mirkhani and
Zainalabedin Navabi, Chapter 94, Test Languages, The VLSI Handbook, Second
Edition (Electrical Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
[12] Naghmeh Karimi and Zainalabedin Navabi, Chapter 95,
Timing Description Languages, The VLSI Handbook, Second Edition (Electrical
Engineering Handbook), CRC Press, 2006, ISBN: 978-0849341991.
PATENTS:
[1]
Z. Navabi, "Timed State Machines:
A Representation for Analysis and Synthesis of Behavioral Descriptions,"
Patent Application Filed with Digital Equipment Corporation, July 1990.
CONFERENCE
PUBLICATIONS:
[1] Z. Navabi with R. Swanson and F. J. Hill, "An
AHPL Compiler/Simulator System," Proceedings of the Sixth Texas Conference
on Computing Systems, November 14 & 15, 1977.
[2] Z. Navabi with F. J. Hill, "Efficient
Simulation of AHPL," Proceedings of the Sixteenth Design Automation
Conference, June 1979, San Diego.
[3] H. A. Kamel with Z. Navabi, "Digitizing for
Computer Aided Finite Element Model Generation," Proceedings of the
ASME Fifth Design Automation Conference, September 1979, St. Louis, Missouri.
[4] F. J. Hill with Z. Navabi, "Extending Second
Generation AHPL Software to Accommodate AHPL III," Proceedings of the
Fourth International Symposium on Computer Hardware Description Languages, pp.
47 53, with F. J. Hill, October 1979, Palo Alto, CA.
[5] Z. Navabi with M. Masud, W. J. Knapp and . J. Hill,
"Impact of VLSI Technology on the Hardware Description Language
AHPL," Proceedings of the IEEE International Conference on Circuits and
Computers, pp. 912 915, October 1980.
[6] C. H. Chiang with Z. Navabi, W. J. Knapp, F. J. Hill
and C. DeSouza, "VLSI Design Automation Using A Hardware Description Language,"
Proceedings of the Phoenix Conference on Computers and Communications, pp. 54 57,
May 1982, Phoenix, Arizona.
[7] F. J. Hill with Z. Navabi and C. H. Chiang,
"Storage Logic Array Realization of RTL Descriptions," Proceedings of
the Sixth International Symposium on Computer Hardware Description Languages,
pp.153 163, May 1983, Pittsburgh, Pennsylvania.
[8] Z. Nava
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