Design Computer Science
Resume:
Yuan Xie, Curriculum Vitae, p. * of **
Yuan Xie
Associate Professor
Department of Computer Science and Engineering
Pennsylvania State Unniversity
354E IST Building, University Park, PA, 16802
*******@***.***.***
http://www.cse.psu.edu/ yuanxie/
Education
Princeton University Princeton, NJ
2002
Ph.D. in Electrical Engineering
Princeton University Princeton, NJ
1999
M.S. in Electrical Engineering
Tsinghua University Beijing, P.R.China
1997
B.S in Electronic Engineering
Professional Experience
2008 - present Pennsylvania State University University Park, PA
Associate Professor in the Department of Computer Science Engineering
Peking University Beijing, China
2010
Adjunct Professor in the Center for Energy-E cient Computing and Application
National Tsing Hua University HsinChu, Taiwan
2010
Visiting Professor in the Department of Computer Science
IMEC (Interuniversity Microelectronics Centre) Leuven, Belgium
05-06/2010
Visiting Researcher
Pennsylvania State University University Park, PA
2003 - 2008
Assistant Professor in the Department of Computer Science Engineering
IBM Microelectronic Division Essex Juction, Vermont
2002 - 2003
Advisory Engineer in Worldwide Design Center
Research Summary
Yuan Xie has published 30+ journals and more than 100 refereed conference papers in the areas of VLSI design, EDA, computer
architecture, and embedded systems, with a focus on design automation and novel architecture for Three-dimensional IC Design
(3D ICs), emerging memory technologies, low power and thermal-aware design, system-level synthesis and high-level synthesis
for embedded systems. He has graduated 10 Ph.D. students and is currently supervising 12 Ph.D. graduates. He has served
as PI/Co-PI on 11 research grants administered by US Federal agencies (including National Science Foundation, DoE, and
DARPA) and 13 research grants from industry, with total amount of $8.65 million and personal share of $3.62 million. These
projects have resulted in the design of new CAD tools and optimizations, and novel architectures for emerging technologies
such as 3D ICs and emerging memory technologies. He has received Best Paper Awards (ISLPED 2011, ASP-DAC 2008,
ASICON 2001) with several Best Paper Nominations(ICCAD 2006, ASP-DAC 2009, ASP-DAC 2010). Through extensive
collaboration with industry partners (IBM, HP, Qualcomm, Honda, Toyota, Seagate, IMEC etc.), he has helped transition
research ideas to industry.
Service Summary
Yuan Xie has been active volunteer in the design automation, VLSI and computer architecture conferences. He served as
program committee member, track chair and conference chair for leading conferences in these areas, including top EDA
conferences such as DAC, ICCAD, ASP-DAC, and DATE (He will serve as the TPC Vice-chair for ASP-DAC 2012, TPC chair
for ISLPED 2013, and TPC chair for ASP-DAC 2013), and top architecture conferences such as ISCA and HPCA. Currently
he serves as a committee member in IEEE Design Automation Technical Committee (DATC), and serves as the Associate
Editor for IEEE Transactions on CAD, IEEE Transactions on VLSI, ACM Journal of Emerging Technologies in Computing
Systems, IEEE Design and Test of Computers, and IET Computers and Design Techniques. He has given 17 tutorials in
prestigious conferences and 50+ invited talks in industry/academia to promote the awareness of 3D IC technology.
Awards and Honors
ACM/IEEE International Symposium on Low Power Electronics Best Paper Award(Paper [C8])
2011
ACM Student Research Competition Grand Finals by advisee Xiangyu Dong
2011
Overseas and Hong Kong, Macau Scholars Collaborative Research Award by China NSF
2010
Association for Computing Machinery(ACM) Distinguished Speaker
2010-
IEEE Computer Society Distinguished Visitor
2010-13
ASP-DAC 2010 Best Paper Award Nomination (Paper [C37])
2010
Selected as one of the 7 overseas scholars in Dragon Star Program supported by China NSF.
2009
Penn State Engineering Society Outstanding Research Award Nomination, Penn State
2009
ASP-DAC 2009 Best Paper Award Nomination (Paper [C51])
2009
IBM Faculty Award
2008
ASP-DAC 2008 Best Paper Award (Paper [C65])
2008
Department Faculty Teaching Award, Computer Science and Engineering Department
2008
Outstanding Teaching Award Nomination, College of Engineering, Penn State
2007
National Science Foundation Faculty Early Career Development (CAREER) Award.
2006
Chun-Hui Outstanding Overseas Scholar Award, Chinese Ministry of Education
2006
ICCAD 2006 Best Paper Award Nomination (Paper [C80]).
2006
SRC(Semiconductor Research Corporations) Inventor Recognition Award.
2002
International Conference on ASICs, Best Paper Award (Paper [C126]).
2001
Research Grants
Research Grants from Federal Agency
National Science Foundation (NSF): EAGER: SHF: Harnessing Cross-Layer Heterogeneity for Future
09/2011-
CMPs. co-PI, $300,000.
08/2012
Department of Energy (DoE): Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in
01/2011-
Exascale Systems. Co-PI with ORNL, HP Labs, Univ. of Michgan, $3,000,000 ($457K to Penn State).
12/2014
National Science Foundation (NSF): CCF: Collaborative Research:Testing and Design-for-Testability
09/2010-
Solutions for 3D Stacked Integrated Circuits. PI, $200,000 (Total $400K shared with Duke University).
09/2013
National Science Foundation (NSF): CCF 905365: Providing Predictable Timing for Task Migration in
09/2009-
Embedded Multi-Core Environments (TiME-ME). PI, $335,000 (Total $1025K shared with NCSU and SIU).
09/2013
National Science Foundation (NSF): CCF 916887: TC:Small:Improving Lifetime Reliability for Recon g-
09/2009-
urable Embedded Systems. co-PI, $414,000
09/2013
National Science Foundation (NSF) and SRC: CCF 903432: ADAMS: Architecture and Design Automa-
08/2009-
tion for 3D Multi-core Systems. PI(with V. Narayanan), $480,000.
08/2012
National Science Foundation (NSF): CNS 0720659: Hybrid Timing Analysis via Multi-mode Execution.
08/2007-
Sole PI, $136,000.
08/2009
National Science Foundation (NSF): CCF 0702617: HoDoo: Holistic Design of On-chip Interconnects.
07/2007-
Co-PI (with C. Das and N. Vijaykrishnan), $630,894.
07/2010
National Science Foundation (NSF) CAREER 0643902: Process Variation Aware Embedded MPSoC
01/2007-
Synthesis.
01/2012
Sole PI, $428,000, plus $270,000 PennState match.
National Science Foundation (NSF): CNS 0454123: SEAT: Soft Error Analysis Toolset.
09/2005-
Co-PI (with N. Vijaykrishnan, M. J. Irwin, and K. Unlu) $433,122.
09/2008
DARPA: Technology and Design Infrastructure for High Performance Three-Dimensional ICs.
09/2006-
Sole PI, $150,000.
03/2008
Research Grants from Industry
Semiconductor Research Corporations (SRC): Test and Design-for-Testability Solutions for 3D Stacked
01/2011-
Integrated Circuits.PI, $96,000.
12/2013
Industrial Technology Research Institute(ITRI, Taiwan): 3D Architecture for intelligent Signal
01/2010-
Processing Architecture (iSPA).PI, NT$50,000.
12/2010
Semiconductor Research Corporations (SRC) : ADAMS: Architecture and Design Automation for 3D
08/2009-
Multi-core Systems. PI(with V. Narayanan), $120,000.
08/2012
Semiconductor Research Corporations (SRC): Statistical Behavioral Synthesis for Nanometer VLSI.
04/2008-
Sole PI, $195,000.
03/2011
Industrial Technology Research Institute(ITRI, Taiwan): Three-Dimensional Architecture Toolset.
12/2009-
Sole PI, $50,000.
12/2010
IBM (Faculty Award): Three-Dimensional Custom EDA Toolset.
07/2008-
Sole PI, gift $20,000.
06/2009
Qualcomm: Three-Dimensional Architecture.
07/2008-
Sole PI, $50,000(gift).
06/2009
Qualcomm: STT-RAM Memory Architecture for Mobile Computing.
01/2010-
Sole PI, $75,000.
06/2011
Honda Research Institute: Three-Dimensional ICs Design.
07/2007-
Sole PI, $105,600.
07/2009
Toyota ITC: Fault-tolerant System Design.
09/2007-
Co-PI (with N. Vijaykrishnan), gift $60,000.
09/2008
The Technology Collaborative (TTC): Digital Sandbox Course Collaboration Grant.
07/2006-
Sole PI, $27,330.
12/2006
The Technology Collaborative (TTC): Embedded Hardware Face Detection of Classi cation.
1/2005-
Co-PI (with N. Vijaykrishnan and H. Raju, R. Sharma), $256,392.
12/2005
The Technology Collaborative (TTC): Transaction Level Power Modeling Methodology.
09/2004-
Co-PI (with N. Vijaykrishnan and M.Kandemir), $149,903 plust $80,000 match from IBM.
3/2006
Journal Publications
[J1]. Vinay Saripalli, Guangyu Sun, Asit Mishra, Yuan Xie, Suman Datta, Vijaykrishnan Narayanan. Exploiting Heterogene-
ity for Energy E ciency in Chip Multiprocessors. To appear in IEEE Journal on Emerging and Selected Topics in Circuits
and Systems (JETCAS), 2011
[J2]. Yuan Xie. Modeling, Architecture, and Applications for Emerging Non-volatile Memory Technologies. To appear in
IEEE Computer Design and Test, January, 2011
[J3]. Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Li. Stacking MRAM atop Microprocessors: An Architecture-
Level Evaluation. To appear in IET Computers and Digital Techniques (IET CDT), June, 2011
[J4]. Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norm Jouppi. Hybrid Checkpointing using Emerging Non-Volatile
Memories for Future Exascale Systems. To appear in ACM Transactions on Architecture and Code Optimization (TACO),
2011
[J5]. Xiaoxia Wu, Wei Zhao, Chandra Nimmagadda, Durodami Lisk, Mark Nakamoto, Sam Gu, Riko Radojcic, Matt Nowak,
and Yuan Xie. Electrical Characterization for Inter-tier Connections and Timing Analysis for 3D ICs. To appear in IEEE
Transactions on Very Large Scale Integrated Systems (TVLSI).
[J6]. Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios Serpanos, Yuan Xie, N. Vijaykrishnan. Power Analysis Attack
Resistance Engineering by Dynamic Voltage and Frequency Scaling. To appear in ACM Transactions in Embedded Computing
Systems (TECS)
[J7]. Yu Wang, Hong Luo, Ku He, Rong Luo, Huanzhong Yang, Yuan Xie. Temperature-Aware NBTI Modeling and the
Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation. To appear in IEEE Transactions on
Dependable and Secure Computing (TDCS).
[J8]. Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. Leakage Power and Circuit Aging
Optimization by Gate Replacement Techniques. To appear in IEEE Transactions on Very Large Scale Integration Systems
(TVLSI).
[J9]. Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie. Hybrid Cache Architecture with Disparate Memory
Technologies. To appear in ACM Transactions on Architecture and Code Optimization (TACO).
[J10]. Feng Wang, Yibo Chen, Xiaoxia Wu, C. Nicopoulos, Yuan Xie, N. Vijaykrishnan. Variation-aware Task Allocation
and Scheduling for MPSoC. IEEE Transactions on CAD (TCAD), Vol 30, No.2, pp. 259-307, 2011
[J11]. Feng Wang and Yuan Xie. SER Analysis for Combinational Logic Using an Accurate Electrical Masking Model.
IEEE Transactions on Dependable and Secure Computing (TDCS). Vol. 8, No. 1, 2011, pp.137-146.
[12]. Xiangyu Dong, Jishen Zhao, Yuan Xie. Cost Analysis and Cost-driven Design for 3D ICs. IEEE Transactions on CAD
(TCAD), Vol 29, No. 12, pp. 1959-1972, Dec. 2010.
[13]. Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, and Kaushik Roy. Variable-Latency Adder (VL-
Adder) Designs for Low Power and NBTI Tolerance. IEEE Transactions on VLSI (TVLSI), Vol 18, No. 11, pp. 1621-1624,
Nov. 2010.
[J14]. Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie. Test-access mechanism optimization for core-based
three-dimensional SOCs. Microelectronics Journal, Volume 41 Issue 10, pp. 601-615, Oct. 2010
[J15]. Gabe Loh, Yuan Xie. 3D Stacked Microprocessor: Are We There Yet? IEEE Micro, Volume 30 Issue 3, pp. 60-64,
May. 2010
[J16]. Wei-lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut Kandemir, and Mary Jane Irwin. Total Power Optimiza-
tion for Combinational Logics Using Genetic Algorithms. Journal of VLSI Signal Processing. Vol. 58, No. 2, pp.145-160,
Feb. 2010.
[J17]. Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie. Temperature-aware NBTI Modeling Techniques in Digital
Circuits. IEICE Transactions on Electronics., No. 6, pp. 875-886, 2009
[J18]. Yuan Xie and Yibo Chen. Statistical High Level Synthesis Considering Process Variations. IEEE Computer Design
and Test, Special Issue on HLS, Vol. 26, Issue 4, pp.78-87, July-August, 2009
[J19]. Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie. Scan-chain design and optimization for three-
dimensional integrated circuits. ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 5, Issue 2,
pp.1-26, July, 2009
[J20]. M. DeBole, R. Krishnan, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao and N. Vijaykrishnan. New-Age:
A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. International Journal
of Parallel Programming., Vol. 37, No.4, pp.417-431, August, 2009.
[J21]. M. Mutyam, A. Mupid, F. Wang, N. Vijaykrishnan, Yuan Xie, M. Kandemir. Process Variation Aware Adaptive
Cache Architecture and Management. IEEE Transactions on Computers., Vol. 58, No.7, pp.865-877, July, 2009.
[J22]. R. Rajaraman, V. Degalahal, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin. Modeling Soft Errors at Device and
Logic Level for Combinational Circuits. IEEE Transactions on Dependable and Secure Computing (TDCS)., Vol. 6, No. 3,
pp.202-216, June 2009.
[J23]. C. Celik, K.Unlu, K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, M. J. Irwin, Y. Xie. Thermal Neutron Induced
Soft Error Rate Measurement in Semiconductor Memories and Circuits. Journal of Radioanalytical and Nuclear Chemistry.,
Vol. 278, No.2, pp.509-512, Nov 2008.
[J24]. S. Srinivasan, R. Krishnan, P. Mangalagiri, Yuan Xie, and N. Vijaykrishnan. Towards Increasing FPGA Lifetime.
IEEE Transactions on Dependable and Secure Computing (TDCS), Vol. 5, Issue 2, pp.115-127 Apr-Jun 2008.
[J25]. Shengqi Yang, W. Wang, W. Wolf, Yuan Xie, N. Vijaykrishnan. Case Study of Reliability-Aware and Low-Power
Design. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 16, Issue 7, pp.861-873, July 2008.
[J26]. Yuh-fang Tsai, Feng Wang, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin. Design Space Exploration for Three-
Dimensional Cache. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.16, Issue 4, pp.444-455, Apr.
2008 .
[J27]. Chang-hong Lin, Yuan Xie, and W.Wolf. Code Compression for VLIW Embedded Systems Using a Self-Generating
Table. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15. No. 10.,pp.1160-1171, Oct. 2007
[J28]. Feng Wang, Mike Debole, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin. On-chip Bus Thermal Analysis
and Optimization. IET Computer and Digital Techniques, Vol. 1, No. 5., pp.590-599, 2007.
[J29]. Yuan Xie, W.Wolf, and H. Lekatsas. Decompression Unit Design for VLIW Embedded Processors. IEEE Transactions
on Very Large Scale Integration Systems (TVLSI), Vol. 15. No. 8, pp.975-980, Aug. 2007.
[J30]. Gabriel Loh, Yuan Xie, and Bryan Black. Processor Design in Three-Dimensional Die-Stacking Technologies. IEEE
Micro, Vol. 27. No. 3, pp.31-48, May/June 2007.
[J31]. Yuan Xie, Lin Li, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Reliability-Aware Co-synthesis for Embedded
Systems. Journal of VLSI Signal Processing, Vol. 49, No.10, pp.87-99, March 2007.
[J32]. Yuan Xie, Wei-lun Hung. Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-
on-Chip (MPSoC) Design. Journal of VLSI Signal Processing, Vol. 45, No. 3, pp.177-189, December 2006.
[J33]. Yuan Xie, Gabriel Loh, Bryan Black, and Kerry Bernstein. Design Space Exploration for 3D Architecture. ACM
Journal of Emerging Technologies for Computer Systems, Vol. 2. No. 2, pp.65-103, April 2006.
[J34]. N. Vijaykrishnan and Yuan Xie. Reliability Concerns in Embedded System Designs. IEEE Computer, Vol. 39, No.
1, pp.118-120, January 2006.
[J35]. Yuan Xie, W.Wolf, and H. Lekatsas. Code Compression Using Variable-to- xed Coding. IEEE Transactions on Very
Large Scale Integration Systems (TVLSI), Vol. 14. No. 5, pp.525-536, January. 2006.
[J36]. Yuan Xie, Jiang Xu, W.Wolf. Augmenting Platform-based Design with Synthesis Tools. Journal of Circuits, Systems
and Computers, Vol. 14. No. 5, pp.525-536, April. 2003.
Book
[1]. Yuan Xie, Jason Cong, Sachin Sapatnekar. Three-dimensional IC: Design, CAD, and Architecture. Springer. 2009
Book Chapters
[1]. Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan. Thermal-aware 3D IC Designs. 3D Integration of Integrated Circuits. Edited
by C. S. Tan, K. N. Chen and S. J. Koester, Pan Stanford Publishing Ltd. 2011
[2]. Yuan Xie, N. Vijaykrishnan, Chita Das. 3D Network-on-chip Architecture. Three-dimensional IC: Design, CAD, and
Architecture. Edited by Yuan Xie, Jason Cong, Sachin Sapatnekar. Springer. 2009.
[3]. Yuan Xie, Xiangyu Dong. System-level Cost Analsysis and Design Exploration for 3D ICs. Three-dimensional IC:
Design, CAD, and Architecture. Edited by Yuan Xie, Jason Cong, Sachin Sapatnekar. Springer. 2009.
[4]. Degalahal, V., R. Ramanarayanan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. E ect of Power Optimizations on Soft
Error Rate. IFIP Series on VLSI-SoC. pp. 1-20, 2006. Edited by R. Reis. Springer.
Refereed Conference Publications
[C1]. Dimin Niu, Yang Xiao, Yuan Xie Low Power Memristor-Based ReRAM Design with Error Correcting Code, To
appear in Proceedings of ACM/IEEE Asia and South-Paci c Design Automation Conference, 2012, 99 accepted out of 288
submissions (34%)
[C2]. Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie Thermal-aware Power Network
Design for IR Drop Reduction in 3D ICs, To appear in Proceedings of ACM/IEEE Asia and South-Paci c Design Automation
Conference, 2012, 99 accepted out of 288 submissions (34%)
[C3]. Qiaosha Zou, Yibo Chen, Alan Su, Yuan Xie System-level Design Space Exploration for 3D SoCs, To appear in
Proceedings of ACM/IEEE CODES+ISSS, 2011, (Invited Paper)
[C4]. Jishen Zhao, Cong Xu, Yuan Xie Bandwidth-Aware Recon gurable Cache Design with Hybrid Memory Technologies,
To appear in Proceedings of ACM/IEEE Intl. Conf. on Computer-aided Design (ICCAD), 2011
[C5]. Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak and Yuan Xie Device-Architecture Co-Optimization
of STT-RAM Based Memory for Low Power Embedded System, To appear in Proceedings of ACM/IEEE Intl. Conf. on
Computer-aided Design (ICCAD), 2011
[C6]. Guangyu Sun, Eren Kursun, Jude Rivers, Yuan Xie Improving the Vulnerability of CMPs to Soft Erros with 3D Stacked
Non-volatile Memory, To appear in Proceedings of ACM/IEEE Intl. Conf. on Computer Design (ICCD), 2011
[C7]. Jue Wang, Xiangyu Dong, Guanyu Sun, Dimin Niu and Yuan Xie. Energy-E cient Multi-Level Cell Phase-Change
Memory System with Data Encoding, To appear in Proceedings of ACM/IEEE Intl. Conf. on Computer Design (ICCD),
2011
[C8]. Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie Analysis and Mitigation of Lateral Thermal
Blockage E ect of Through-Silicon-Via in 3D IC Designs, Proceedings of ACM/IEEE Intl. Symp. on Low Power Electronc
Devices (ISLPED), 2011, Best Paper Award
[C9]. Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu F2 BFLY: An On-Chip Free-Space Optical Network
with Wavelength-Switching, Proceedings of ACM/IEEE 25th International Conference on Supercomputing (ICS), 2011, (35
accepted out of 161 submissions, 21%)
[C10]. A. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, N. Vijaykrishnan, C. Das Architecting NoCs for Stacked 3D
STT-RAM Caches in CMPs, Proceedings of ACM/IEEE International Conference on Computer Architecture (ISCA), 2011,
(40 accepted out of 208 submissions, 19%)
[C11]. Guangyu Sun, C. Hughes, C. Kim, Jishen Zhao, C. Xu, Yuan Xie, Yen-KuanChen Moguls: a Model to Explore Mem-
ory Hierarchy for Throughput Computing, Proceedings of ACM/IEEE International Conference on Computer Architecture
(ISCA), 2011,(40 accepted out of 208 submissions, 19%)
[C12]. Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Vijaykrishnan Narayanan, Yuan Xie, Suman Dutta Au-
tomated Mapping for Recon gurable Single Electron Transistor Arrays, Proceedings of ACM/IEEE Design Automation
Conference (DAC), 2011
[C13]. Cong Xu, Xiangyu Dong, Norm Jouppi, and Yuan Xie Design Implications of Memristor-Based RRAM Cross-Point
Structures, In Proceedings of ACM/IEEE Design Automation and Test in Europe Conference (DATE), pp.734-739, 2011
[C14]. Jishen Zhao, Xiangyu Dong, and Yuan Xie An Energy-E cient 3D CMP Design with Fine-Grained Voltage Scaling,
In Proceedings of ACM/IEEE Design Automation and Test in Europe Conference (DATE), pp.539-542, 2011
[C15]. Shekhar SriKantaiah, Emre Kultursay, Tao Zhang, Mahmut Kandemir, Mary Jane Irwin, and Yuan Xie, MorphCache:
A Recon gurable Adaptive Multi-level Cache Hierarchy for CMPs, Proceedings of IEEE International Symposium on High-
Performance Computer Arhitecture Conference (HPCA), pp. 231-242, 2011
[C16]. Jin Ouyang and Yuan Xie Enabling Quality-of-Service in Nanophotonic Network-on-Chip, Proceedings of ACM/IEEE
Asia and South Paci c Design Automation Conference (ASP-DAC 2011), 2011
[C17]. Xiangyu Dong and Yuan Xie AdaMS: Adaptive MLC/SLC Phase-Change Memory Design for File Storage, Proceed-
ings of ACM/IEEE Asia and South Paci c Design Automation Conference (ASP-DAC), pp.31-36, 2011
[C18]. Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang On-Chip Hybrid Power Supply System
for Wireless Sensor Nodes, Proceedings of ACM/IEEE Asia and South Paci c Design Automation Conference (ASP-DAC),
pp.43-48, 2011
[C19]. Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie A Frequent-Value Based PRAM Memory Architecture, Proceedings
of ACM/IEEE Asia and South Paci c Design Automation Conference (ASP-DAC), pp.211-216, 2011
[C20]. Jin Ouyang and Yuan Xie LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support,
Proceedings of Intl. Symp. on Microarchitecture (MICRO 2010), pp.351-356, 2010
[C21]. Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng,
Yong-long Lin, A 3D SoC Design for H.264 Application With On-Chip DRAM Stacking, Proceedings of IEEE International
3D System Integration Conference (3DIC), 2010
[C22]. Jing Xie, Xiangyu Dong, Yuan Xie 3D Memory Stacking for Fast Checkpointing/Restore Applications, Proceedings
of IEEE International 3D System Integration Conference (3DIC), 2010
[C23]. Tao Zhang, Kui Wang, Yi Feng, Lian Duan, Xiaodi Song, Yuan Xie, Xu Cheng, Yong-long Lin, A Customized Design
of DRAM Controller for On-Chip 3D DRAM Stacking, Proceedings of Custom IC Conference (CICC 2010), 2010
[C24]. Xiangyu Dong, Yuan Xie, Norm Jouppi, Naveen Muralimanohar Simple but E ective Heterogeneous Main Memory
with On-Chip Memory Controller Support Proceedings of Supercomputing (SC 2010), 2010.
[C25]. Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu Modeling TSV Open Defects in 3D-Stacked DRAM, Proceedings
of Int. Conf. on Testing (ITC 2010), Nov, 2010.
[C26]. Matt Poremba, Yuan Xie, Marilyn Wolf. Accelerating Adaptive Background Subtraction with GPU and CBEA
Architecture, Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), pp.305-310, Oct. 2010.
[C27]. Jin Ouyang, Jing Xie, Matt Poremba, Yuan Xie Design Methodology of 3D Network-on-Chip with Inductive/Capacitive-
Coupling Vertical Interconnect Proceedings of Int. Conf. on CAD (ICCAD), Nov, 2010.
[C28]. Yibo Chen, Dimin Niu, Yuan Xie, Krish Chakrabarty Cost-E ective Integration of Three-Dimensional (3D) ICs
Emphasizing Testing Cost Analysis Proceedings of Int. Conf. on CAD (ICCAD), Nov, 2010.
[C29]. Yibo Chen, Jishen Zhao, Yuan Xie 3D-NonFAR: Three-Dimensional Non-Volatile FPGA ARchitecture Using Phase
Change Memory. Proceedings of Intl. Symp. Low Power Electronic Devices (ISLPED). August, 2010. (25% acceptance rate).
[C30]. Dimin Niu, Yiran Chen, Yuan Xie Dual-element Memristor-Based Memory Design. Proceedings of Intl. Symp. Low
Power Electronic Devices (ISLPED). August, 2010. (25% acceptance rate).
[C31]. Jishen Zhao, Xiangyu Dong, Yuan Xie Cost-Aware Three-Dimensional (3D) Many-Core Multiprocessor Design.
Proceedings of Design Automation Conference (DAC). 2010. (24% acceptance rate).
[C32]. Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie Impact of Process Variations on Emerging Memristor. Proceedings of
Design Automation Conference (DAC). 2010. (24% acceptance rate).
[C33]. Xiaoxia Wu, Guangyu Sun, Reetuparna Das, Yuan Xie, Jian Li, Chita R. Das Cost-driven 3D Integration with
Interconnect Layers. Proceedings of Design Automation Conference (DAC). 2010. (24% acceptance rate).
[C34]. Yongsoo Joo, Dimin Niu, Guangyu Sun, Xiangyu Dong, Yuan Xie Energy- and Endurance-Aware Design of Phase
Change Memory Caches. Proceedings of Design Automation and Test in Europe (DATE). 2010. (25% acceptance rate).
[C35]. Guangyu Sun, Yongsoo Joo, Yibo Chen, Yuan Xie, Yiran Chen, Helen Li A Hybrid Solid-State Storage Architecture
for Performance, Energy Consumption and Lifetime Improvement. Proceedings of High Performance Computer Architecture
(HPCA). 2010. (18% acceptance rate).
[C36]. Yuan Xie Processor Architecture Design Using 3D Integration Technology.(Invited Paper) Proceedings of VLSI
Design. 2010.
[C37]. Yibo Chen, Yu Wang, Yuan Xie, Andres Takach Parametric Yield Driven Resource Binding in Behavioral Synthesis
with Multi-Vth/Vdd Library. Proceedings of Asia and South-Paci c Design Automation Conference (ASP-DAC). 2010. (33%
acceptance rate(115/340)) (Best Paper Nomination).
[C38]. Yibo Chen, Yu Wang, Yuan Xie, Andres Takach Minimizing Leakage Power in Aging-Bounded High-level Synthesis
with Design Time Multi-Vth Assignment. Proceedings of Asia and South-Paci c Design Automation Conference (ASP-DAC).
2010. (33% acceptance rate(115/340)).
[C39]. Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie Energy and Performance Driven Circuit Design for Emerging Phase-
Change Memory. Proceedings of Asia and South-Paci c Design Automation Conference (ASP-DAC). 2010. (33% acceptance
rate(115/340)).
[C40]. Paul Falkstern, Yao-wen Chang, Yuan Xie, Yu Wang Three Dimensional Integrated Circuit (3D IC) Floorplan and
Power/Ground Network Co-synthesis. Proceedings of Asia and South-Paci c Design Automation Conference (ASP-DAC).
2010. (33% acceptance rate(115/340)).
[C41]. Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, Yuan Xie Leveraging 3D PCRAM Tech-
nologies to Reduce Checkpoint Overhead for Future Exascale Systems. Proceedings of International Conference on High
Performance Computing, Networking, Storage and Analysis (SC). 2009. (22% acceptance rate(59/261)).
[C42]. Xiangyu Dong, Norm Jouppi, Yuan Xie PCRAMsim: System-Level Performance, Energy, and Area Modeling for
Phase-Change RAM. Proceedings of International Conference on Computer-Aided Design (ICCAD). 2009. pp 269-275.
(26% acceptance rate(115/438)).
[C43]. Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie Intrinsic NBTI-Variability Aware Statistical Pipeline Performance
Assessment and Tuning. Proceedings of International Conference on Computer-Aided Design (ICCAD). 2009. pp 164-171.
(26% acceptance rate(115/438)).
[C44]. Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie. Hybrid Cache Architecture with Disparate Memory
Technologies. Proceedings of International Symposium on Computer Architecture (ISCA), pp.34-45, June. 2009.
[C45]. Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. Gate Replacement Techniques for
Simultaneous Leakage and Aging Optimization. Proceedings of Design Automation and Test in Europe (DATE), pp. 324-333.
April. 2009.
[C46]. Balaji Vaidyanathan, Anthony Oates, Yuan Xie, Yu Wang. NBTI-Aware Statistical Circuit Delay Assessment.
Proceedings of Intl. Symp. on Quality Electronics Device (ISQED), March. 2009.
[C47]. Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang. On the e cacy
of Input Vector Control to mitigate NBTI e ects and leakage power. Proceedings of Intl. Symp. on Quality Electronics Device
(ISQED), March. 2009.
[C48]. Luca P. Carloni, Partha Pande, and Yuan Xie . Networks-on-chip in emerging interconnect paradigms: Advantages
and challenges. Proceedings of 3rd ACM/IEEE Intl. Symp. on Networks-on-chip, pp. 93-102. May. 2009.
[C49]. Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie. Power and Performance of Read-write aware hybrid caches
with non-volatile memories. Proceedings of Design Automation and Test in Europe (DATE), pp. 737-742. April. 2009.
[C50]. Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen. A Novel MRAM Stacking Architecture for Chip-
multiprocessors (CMP). Proceedings of High Performance Computer Architecture (HPCA), pp. 239-249. Feb. 2009. (19%
acceptance rate(34/185)).
[C51]. Xiangyu Dong and Yuan Xie. System-level Cost Analysis and Design Exploration for 3D ICs. Proceedings of Asia-
South Paci c Design Automation Conference (ASP-DAC), Jan. 2009. Best Paper Award Nomination. (32% acceptance
rate(116/355)).
[C52]. Mike Debole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan A Criticality-Driven Microarchitectural Three
Dimensional (3D) Floorplanner. Proceedings of Asia-South Paci c Design Automation Conference (ASP-DAC), Jan. 2009.
(32% acceptance rate(116/355)).
[C53]. Feng Wang, Andres Takach, and Yuan Xie. Variation-Aware Resource Sharing and Binding in Behavioral Synthesis.
Proceedings of Asia-South Paci c Design Automation Conference (ASP-DAC), Jan. 2009. (32% acceptance rate(116/355)).
[C54]. Yibo Chen and Yuan Xie. Tolerating Process Variations in High-Level Synthesis Using Transparent Latches. Pro-
ceedings of Asia-South Paci c Design Automation Conference (ASP-DAC), Jan. 2009. (32% acceptance rate(116/355)).
[C55]. Mike Debole, Wenping Wang, Yu Wang, Yuan Xie, Vijay Nayaranan, Yu Cao. A Framework for Estimating NBTI
Degradation of Microarchitectural Components Proceedings of Asia-South Paci c Design Automation Conference (ASP-
DAC), Jan. 2009. (32% acceptance rate(116/355)).
[C56]. P. Mangalagiri, S. Bae, R. Krishnan, Yuan Xie, N. Vijaykrishnan. Thermal-Aware Reliability Analysis for Platform
FPGAs Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 722-727, Nov. 2008. (122 out of
458 submissions, 27% acceptance rate).
[C57]. Xiaoxia Wu, Yibo Chen, Krish Chakrabarty, and Yuan Xie. Test-Access Mechanism Optimization for Core-Based
Three-Dimensional SOCs. Proceedings of International Conference on Computer Design (ICCD), pp.212-218 Oct. 2008.
[C58]. Yibo Chen, Feng Wang, Yuan Xie ILP-based Scheme for Timing Variation-aware Scheduling and Resource Binding
Proceedings of System-on-Chip Conference, pp.27-30, Sept. 2008.
[C59]. Jin Ouyang, Yuan Xie Power Optimization for FinFET-based Circuits Using Genetic Algorithms Proceedings of
System-on-Chip Conference, pp. 211-214, Sept. 2008.
[C60]. Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das
MIRA: A Multi-Layered On-Chip Interconnect Router Architecture Proceedings of International Symopsium on Computer
Architecture (ISCA), June. 2008. (37 out of 259 submissions, 14% acceptance rate)
[C61]. Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen Circuit and Microarchitecture Evaluation
of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Proceedings of Design Automation Conference (DAC),
pp.554-559, June. 2008. (138 out of 639 submissions, 21% acceptance rate)
[C62]. Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam Thermal-aware Design Considerations for
Application-Speci c Instruction Set Processor in Proceedings of International Symposium on Appication Speci c Processors,
June. 2008. (19 out of 64 submissions, 29% acceptance rate)
[C63]. Xiangyu Dong, Xiaoxia Wu, Yuan Xie Cost Analysis and Cost-driven EDA ow for 3D ICs in Proceedings of 3D-SIC
Conference, May. 2008.
[C64]. Feng Wang, Guangyu Sun, Yuan Xie. A Variation Aware High Level Synthesis Framework. Proceedings of Design
Automation and Test in Europe (DATE),pp.1063-1068, Mar. 2008. (198 out of 839 submissions, 23% acceptance rate)
[C65]. Feng Wang, Xiaoxia Wu, Yuan Xie. Variability-Driven Module Selection with Joint Design Time Optimization and
Post-Silicon Tuning. To appear in Proceedings of Asia-South Paci c Design Automation Conference (ASP-DAC), Jan. 2008.
Best Paper Award. (29% acceptance rate for regular papers (100/351)).
[C66]. Feng Wang, Xiaoxia Wu, C. Nicopoulos, Yuan Xie, N. Vijaykrishnan. Variation-aware Task Allocation and Scheduling
for MPSoC. Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 138-149, Nov. 2007. (139
out of 510 submissions, 27% acceptance rate).
[C67]. Xiaoxia Wu, Paul Falkenstern, and Yuan Xie. Scan Chain Design for Three-dimentional(3D) ICs. Proceedings of
International Conference on Computer Design (ICCD), pp.208-214, Oct. 2007. (88 out of 259 submissions, 33% acceptance
rate).
[C68]. S. Srinivasan, P. Mangalagiri, Yuan Xie, N. Vijaykrishnan. FPGA Routing Architecture Analysis Under Variations.
Proceedings of International Conference on Computer Design (ICCD), pp.152-157, Oct. 2007. (88 out of 259 submissions,
33% acceptance rate).
[C69]. H. Luo, Y. Wang, K. He, R. Luo, H. Yang, and Yuan Xie. A Novel Gate-level NBTI Delay Degradation Model with
Stacking E ect. To appear in Proceedings of International Workshop on Power And Timing Modeling, Optimization and
Simulation (PATMOS), Sept. 2007.
[C70]. J. Kim, C. Nicopoulos, D. Park, R. Das, Yuan Xie, N. Vijaykrishnan, C. Das. A Novel Dimensionally-Decomposed
Router for On-Chip Communication in 3D Architectures. Proceedings of the Annual International Symposium on Computer
Architecture (ISCA), pp. 138-149, June 2007. (46 papers accepted out of 204 submissions. 23% acceptance rate)
[C71]. Alex K. Jones, Steven Levitan, Rob A. Rutenbar, and Yuan Xie. Collaborative VLSI-CAD Instruction in the Digital
Sandbox. Proceedings of IEEE International Conference on Microelectronic Systems Education, pp. 141-142, June 2007.
[C72]. Feng Wang, Yuan Xie, and Hai Ju. A Novel Criticality Computation Method in Statistical Timing Analysis.
Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1611-1616, April 2007.
(208 papers accepted out of 933 submissions. 22% acceptance rate)
[C73]. Y. Wang, H. Luo, K. He, R. Luo, Yuan Xie, and H. Yang. Temperature-aware NBTI Modeling and the Impact of
Input Vector Control on Performance Degradation. Proceedings of IEEE International Conference on Design Automation
and Test in Europe (DATE), pp. 546-551, April 2007. (208 papers accepted out of 933 submissions. 22% acceptance rate)
[C74]. R. Krishnan, R. Ramanarayanan, S. Srinivasan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. Variation Impact on SER of
Combinatorial Circuits. Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 911-916,
March 2007. (93 papers accepted out of 292 submissions. 31% acceptance rate)
[C75]. A. Mupid, M. Mutyam, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. Variation Analysis of CAM Cells. Proceedings of
IEEE International Symposium on Quality Electronic Design (ISQED), pp. 333-338, March 2007. (93 papers accepted out of
292 submissions. 31% acceptance rate)
[C76]. H. Luo, Y. Wang, K. He, R. Luo, H. Yang, Yuan Xie. Modeling of PMOS NBTI E ect Considering Temperature
Variation. Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 139-144, March 2007.
(93 papers accepted out of 292 submissions. 31% acceptance rate)
[C77]. Feng Wang and Yuan Xie. Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking
Model. Proceedings of IEEE International Conference on VLSI Design (VLSID), pp. 165-170, Jan. 2007. (141 papers
accepted out of 432 submissions. 32% acceptance rate)
[C78]. Balaji Vaidyanathan, W-L. Hung, Feng Wang, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. Architecting Microprocessor
Components in 3D Design Space. Proceedings of IEEE International Conference on VLSI Design (VLSID), pp. 103-108, Jan.
2007. (141 papers accepted out of 432 submissions. 32% acceptance rate)
[C79]. Balaji Vaidyanathan, Yuan Xie, N. Vijaykrishnan, R. Luo. Leakage Optimized DECAP Design for FPGAs. Proceed-
ings of IEEE Asia Paci c Conference on Circuits and Systems (APCCAS), pp. 560-563, Dec. 2006.
[C80]. Wei-lun Hung, Xiaoxia Wu, Yuan Xie. Guaranteeing Performance Yield in High-Level Synthesis. Proceedings of
International Conference on Computer Aided Design (ICCAD), pp.303-309, Nov. 2006. Best paper award nomination.(130
papers accepted out of 537 submissions. 24% acceptance rate) .
[C81]. Qian Ding, R. Luo, H. Wang, H. Yang and Yuan Xie. Modeling the Impact of Process Variation on Critical Charge
Distribution. Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 243-237, Sept. 2006. (58 regular
papers accepted out of 177 submissions. 31% acceptance rate)
[C82]. Balaji Vaidyanathan and Yuan Xie. Crosstalk-Aware Energy E cient Encoding for Instruction Bus through Code
Compression. Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 93-97, Sept. 2006. (58 papers
accepted out of 177 submissions. 31% acceptance rate)
[C83]. Xiaoxia Wu, Feng Wang, and Yuan Xie. Analysis of Subthreshold Finfet Circuit for Ultra-low Power Design.
Proceedings of IEEE International System-on-Chip Conference (SOCC), pp. 91-93, Sept. 2006.
[C84]. S. Srinivasan, M. Prasanth, S. Karthink, Yuan Xie, N. Vijaykrishnan. FLAW: FPGA Lifetime Awareness. Proceedings
of the 43rd Design Automation Conference (DAC), pp. 630-635, July. 2006. (209 papers accepted out of 865 submissions.
24% acceptance rate)
[C85]. F. Li,C. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan, M. Kandemir. Design and Management of 3D Chip
Multiprocessors using Network-in-memory. Proceedings of the Annual International Symposium on Computer Architecture
(ISCA), pp. 130-141, June. 2006. (31 papers accepted out of 234 submissions. 13% acceptance rate)
[C86]. Feng Wang, Yuan Xie. An Accurate and E cient Model of Electrical Masking E ect for Soft Errors in Combinatorial
Logic. Proceedings of the Second Workshop on System E ects of Logic Soft Errors (SELSE), April 2006.
[C87]. B. Vaidyanathan, Yuan Xie, N. Vijaykrishnan. Soft Error Analysis and Optimizations of C-elements in Asynchronous
Circuits. Proceedings of the Second Workshop on System E ects of Logic Soft Errors (SELSE), April 2006.
[C88]. R. Ramanarayanan, R. Krishnan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. Temperature and Voltage Scaling E ects
on Electrical Masking. Proceedings of the Second Workshop on System E ects of Logic Soft Errors (SELSE), April 2006.
[C89]. Wei-lun Hung, G. Link, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. Interconnect and Thermal-aware Floorplanning
for 3D Microprocessors. Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 98-104, March.
2006. (93 papers accepted out of 256 submissions. 36% acceptance rate)
[C90]. Feng Wang, Yuan Xie, N. Vijaykrishnan and M. J. Irwin. On-chip Bus Thermal Analysis and Optimization.
Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 850-855, March 2006.
(233 papers accepted out of 834 submissions. 28% acceptance rate)
[C91]. Feng Wang, Yuan Xie, K. Bernstein and Y. Luo. Dependability Analysis of Nano-scale FinFET Circuits. Proceedings
of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 399-404, March 2006.
[C92]. M. Mutyam, M. Eze, N. Vijaykrishnan, Yuan Xie. Delay and Energy E cient Data Transmission for On-Chip Buses.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 355-360, March 2006.
[C93]. S. Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie. Reliability-Aware SOC Voltage Islands Partition and Floorplan.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 343-348, March 2006.
[C94]. O. Ozturk, F. Wang, M. Kandemir, Yuan Xie. Optimal Topology Exploration for Application-Speci c 3D Archi-
tectures. Proceedings of Asia and South Paci c Design Automation Conference (ASP-DAC), pp. 390-395, Jan. 2006. (135
papers accepted out of 432 submissions. 31% acceptance rate)
[C95]. Ramanarayanan, R., J. S. Kim, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. SEAT-LA: A Soft Error Analysis tool
for Combinational Logic. Proceedings of IEEE International Conference on VLSI Design, pp. 499-502, Jan. 2006. (26.8%
acceptance rate for regular papers (88 out of 328 submissions))
[C96]. T. Richardson, C. Nicopoulos, D. Park, N. Vijaykrishnan, Yuan Xie, C. R. Das. A Hybrid SoC Interconnect with
Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. Proceedings of IEEE International Conference on
VLSI Design, pp. 499-502, Jan. 2006. (26.8% acceptance rate for regular papers)
[C97]. R. Luo, H. Luo, H. Yang, Yuan Xie. An Instruction Level Analytical Power Model for Designing Low Power SOC.
Proceedings of IEEE International Conference on ASICs, pp.1070-1073, Oct. 2005.
[C98]. T. Richardson and Yuan Xie. Evaluation of Thermal-Aware Design Techniques for Microprocessors. Proceedings of
IEEE International Conference on ASICs, pp.62-65, Oct. 2005.
[C99]. W-L. Hung, G. Link, Yuan Xie, N. Vijaykrishnan, N. Dhanwada, J. Conner. Temperature-Aware Voltage Islands
Architecting in System-on-Chip Design. Proceedings of IEEE International Conference on Computer Design (ICCD), pp.
689-696, Oct. 2005. (101 out of 313 submissions, 32% acceptance rate)
[C100]. S. K. Narayanan, G. Chen, M. Kandemir, Yuan Xie. Temperature-Sensitive Loop Parallelization for Chip Multi-
processors. Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 677-682, Oct. 2005. (101 out
of 313 submissions, 32% acceptance rate)
[C101]. Y-F. Tsai, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. Three-Dimensional Cache Design Exploration Using 3DCacti.
Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 519-524, Oct. 2005. (101 out of 313
submissions, 32% acceptance rate)
[C102]. D. Hostetler and Yuan Xie. Adaptive Power Management in Software Radios Using Resolution Adaptive Analog
to Digital Converters. Proceedings of IEEE International Symposium on VLSI (ISVLSI), pp. 186-191, May. 2005.
[C103]. W-L. Hung, Yuan Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, M. J. Irwin Thermal-Aware Floorplan-
ning Using Genetic Algorithms. Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 634-639,
Mar. 2005. (83 out of 222 submissions, 37% acceptance rate)
[C104]. S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie. An ILP Formulation for Reliability-Oriented
High-Level Synthesis. Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 364-369, Mar.
2005. (83 out of 222 submissions, 37% acceptance rate)
[C105]. S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie. Reliability-Centric Hardware/Software Co-design.
Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 364-369, Mar. 2005. (83 out of 222
submissions, 37% acceptance rate)
[C106]. S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie. Reliability-centric High-level Synthesis. Proceedings of
IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1258-1263, March 2005. ( 176 papers
accepted out of 825 submissions. 21% acceptance rate)
[C107]. S. Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie. Power Attack Resistant Crypto Design: A Dynamic Voltage and
Frequency Switching Approach. Proceedings of IEEE International Conference on Design Automation and Test in Europe
(DATE), pp. 64-69, March 2005. ( 21% acceptance rate)
[C108]. Wei-lun Hung, Yuan Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. Thermal-Aware Allocation and Scheduling
for Systems-on-a-Chip Design. Proceedings of IEEE International Conference on Design Automation and Test in Europe
(DATE), pp. 898-899, March 2005. ( 21% acceptance rate)
[C109]. Y-F Tsai, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. Leakage-Aware Interconnect for On-Chip Network. Proceedings
of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 230-231, March 2005. ( 21%
acceptance rate)
[C110]. J.Conner,Yuan Xie, M. Kandemir, R. Dick, G. Link. FD-HGAC: A Hybrid Heuristic/Genetic Algorithm Hard-
ware/Software Co-synthesis Framework with Fault Detection. Proceedings of the Asia South Paci c Design Automation
Conference (ASP-DAC)., pp. 709-712, Jan. 2005. (99 regular papers accepted out of 692 submissions (14.3%))
[C111]. S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Yuan Xie. Low-Leakage Robust SRAM Cell Design for Sub-100nm
Technologies. Proceedings of the Asia South Paci c Design Automation Conference (ASP-DAC)., pp. 539-544, Jan. 2005.
14.3% acceptance rate for regular papers (99 regular papers accepted out of 692 submissions (14.3%))
[C112]. Y-F. Tsai, N. Vijaykrishnan, M. J. Irwin, Yuan Xie. In uence of Leakage Reduction Techniques on Delay/Leakage
Uncertainty. Proceedings of the 18th International Conference on VLSI Design (VLSID), pp. 374-379, Jan. 2005. (97 regular
papers accepted out of 352 submissions (28%)) .
[C113]. S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Yuan Xie. Accurate Stacking E ect Macro-Modeling of Leakage
Power in Sub-100nm Circuits. Proceedings of the 18th International Conference on VLSI Design (VLSID), pp. 165-170, Jan.
2005. (97 regular papers accepted out of 352 submissions (28%)) .
[C114]. S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Yuan Xie, M. J. Irwin. Improving Soft-error Tolerance
of FPGA Con guration Bits. Proceedings of International Conference on Computer Aided Design (ICCAD), Nov. 2004.
(24% acceptance rate).
[C115]. W-L Hung, C. Addo-Quaye, T. Theocharides, Yuan Xie, N. Vijaykrishnan, M. J. Irwin. Thermal-Aware IP
Virtualization and Placement for Networks-on-Chip Architecture. Proceedings of IEEE International Conference on Computer
Design (ICCD), pp. 430-437, Oct. 2004. (84 out of 226 submissions, 37% acceptance rate.)
[C116]. Yuan Xie, L. Li, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Reliability-aware Cosynthesis for Embedded Systems.
Proceedings of IEEE International Conference on Application-Speci c Systems, Architectures, and Processors (ASAP), pp. 41-
50, Sept. 2004.
[C117]. W-L. Hung,Yuan Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. Total Power Optimization Through Simul-
taneously Multiple-VDD Multiple-VTH Assignment and Device Sizing With Stack Forcing. Proceedings of International
Symposium on Low Power Electronics and Design (ISLPED 2004), pp. 144-149, Aug. 2004. 34% acceptance rate)
[C118]. W. Xu, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. Design of a Nanosensor Array Architecture. Proceedings of Great
Lakes Symposium on VLSI(GLSVLSI), pp. 298-303, Apr. 2004. (23 full papers accepted out of 235 submissions, 10% rate)
[C119]. V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin. The E ect of Threshold Voltages on the
Soft Error Rate. Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 503-508, Mar. 2004.
(49 papers accepted out of 148 submissions, 33%)
[C120]. C-H. Lin, W. Wolf, and Yuan Xie. LZW-based Code Compression for VLIW Embedded Systems. Proceedings
of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 76-81, Feb. 2004. (181 papers
accepted out of 780 submissions (23%))
[C121]. Yuan Xie. Analysis of Two Code Compression Algorithms for Embedded Systems. Proceedings of International
Conference on ASIC (ASICON), pp. 773-776. Oct. 2003.
[C122]. Yuan Xie, Wayne Wolf, H. Lekatsas. Code Compression Using Arithmetic Coding Based Variable-to- xed Coding.
Proceedings of Data Compression Conference(DCC 2003), pp. 382-391, Mar. 2003.
[C123]. Yuan Xie, W. Wolf, and H. Lektasas. Pro le-driven Code Compression. Proceedings of IEEE International Confer-
ence on Design Automation and Test in Europe (DATE), pp. 76-81, Mar. 2003. (152 out of 590 submissions (25%))
[C124]. Yuan Xie, W. Wolf, and H. Lektasas. Code Compression for VLIW Using Variable-to- xed Coding. Proceedings
of Fifteenth International Symposium on System Synthesis (ISSS 2002), pp. 138-143, Oct. 2002. (24 out of 71 submissions
(33%))
[C125]. Yuan Xie, W. Wolf, and H. Lektasas. A Code Decompression Architecture for VLIW Processors. Proceedings of
the Thirty-Fourth International Symposium on Microarchitecture (MICRO-34). pp. 66-75. (29 out of 144 submissions, 20%
acceptance rate)
[C126]. Yuan Xie, W. Wolf, and H. Lektasas. Compression Ratio and Decompression Overhead Tradeo s in Code Com-
pression for VLIW Architectures. Proceedings of the Fourth International Conference on ASIC (ASICON). Best Paper
Award.
[C127]. Yuan Xie, W. Wolf. ASICosyn: Co-Synthesis of Coditional Task Graphs with Custom ASICs. Proceedings of the
Fourth International Conference on ASIC (ASICON).
[C128]. Yuan Xie, W. Wolf. Allocation and Scheduling of Conditional Task Graphs in Co-synthesis. Proceedings of IEEE
International Conference on Design Automation and Test in Europe (DATE), pp. 620-625, Mar. 2001. (81 full papers out of
300 submissions (27%))
[C129]. Yuan Xie, Hua Lin, Zhao Wu, W. Wolf. CAD Techniques for Multimedia System Design. Proceedings of Synthesis
and System Integration of MIxed Technologies (SASIMI), Mar. 2000.
[C130]. Yuan Xie and Wayne Wolf. Co-synthesis with Custom ASICs. Proceedings of the Asia South Paci c Design
Automation Conference (ASP-DAC), pp. 129-134, Jan. 2000.
Patent
[1]. United States Patent. No.7,095,343. Code Compression Algorithms and Architectures for Embedded Systems. Issued
on August 22, 2006.
Student Supervision
Doctoral Dissertations Supervised
Guangyu Sun, Ph.D. in Computer Science and Engineering
2011
Memory Hierarchy Design using Emerging Non-volatile Memories
First Employer: Assistant Professor at Peking University, China.
Xiangyu Dong, Ph.D. in Computer Science and Engineering
2011
Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs
First Employer: Researcher at Qualcomm.
Yibo Chen, Ph.D. in Computer Science and Engineering
2011
Variation-aware Behavioral Synthesis for Nanometer VLSI circuits
First Employer: Researcher at Synopsys Inc.
Mike Debole, Ph.D. in Computer Science and Engineering (co-advise with N. Vijaykrishnan)
2011
Con gurable Accelerators for Video Analytics
First Employer: Post-doc at Penn State.
Soumya Eachempati, Ph.D. in Computer Science and Engineering (co-advise with N. Vijaykrishnan)
2010
In uence of Emerging Technologies on Interconnect Architectures
First Employer: Intel.
Prasanth Mangalagiri, Ph.D. in Computer Science and Engineering (co-advise with N. Vijaykrishnan)
2010
A Reliability and Process Variation Aware Design ow for Platform FPGAS
First Employer: Intel.
Xiaoxia Wu, Ph.D. in Computer Science and Engineering
2010
Design Space Exploration for 3D ICs
First Employer: Qualcomm.
Balaji Vaidyanthan, Ph.D. in Computer Science and Engineering
2009
Reliability Analysis and Optimization for Nanoscale System-on-Chip Design
First Employer: TSMC, Taiwan.
Feng Wang, Ph.D. in Computer Science and Engineering
2008
Design Automation Techniques to Mitigate Process Variations
First Employer: Qualcomm.
Yu Wang, Ph.D. in Electronic Engineering, Tsinghua University (co-advised with Prof. Huazhong Yang)
2007
Optimization for the Leakage Current and Reliability in Digital Integrated Circuits
Current Job: Assistant Professor in Tsinghua University.
Wei-lun Hung, Ph.D. in Computer Science and Engineering
2006
Designing Cool Chips: Low Power and Thermal-Aware Design Methodologies
Current Employer: Sun Microsystems.
Postdoctor Supervised
Yongsoo Joo, Now Assistant Professor at Ewha University, Korea.
Post-Doc
Lian Duan, Ph.D. from Peking University, China.
Post-Doc
Master Thesis Supervised
Paul Falkenstern, M.S. in Computer Science and Engineering
2008
Design Automation Tools for 3D ICs
First job: Lockheed Martin Inc.
Han-wei Chen, M.S. in Computer Science and Engineering (co-advised with N.Vijaykrishnan)
2007
Impact of Circuit Degradation on Design Security of Field Programmable Devices
Now graduate student at University of Texas at Austin.
Charles Addo-Quaye, M.S. in Computer Science and Engineering (co-advised with N.Vijaykrishnan)
2007
Thermal-Aware Placement and Virtualization for Three Dimensional Network-on-Chip Designs
Now Ph.D. student at PennState.
Melvin Eze, M.S. in Computer Science and Engineering (co-advised with N.Vijaykrishnan)
2007
Delay and Energy E cient Data Transmission for On-Chip Buses
Now Ph.D. student at PennState.
Yinkun Xue, M.S. in Computer Science and Engineering
2006
Providing Energy-Aware Map Services to Mobile Devices
First job: Siemens Inc.
Thomas Richardson, M.S. in Computer Science and Engineering
2005
Analysis and Design of Scalable SoC Interconnects
First job: Availink Inc.
Current Students
Jin Ouyang, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2012
Ph.D.
Dimin Niu, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2013
Ph.D.
Tao Zhang, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2013
Ph.D.
Jing Xie, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2014
Ph.D.
Jishen Zhao, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2014
Ph.D.
Cong Xu, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2014
Ph.D.
Qiaosha Zou, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2015
Ph.D.
Matthew Poremba, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2015
Ph.D.
Hsiang-Yun Cheng, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2015
Ph.D.
Jue Wang, Ph.D. in Computer Science and Engineering, expected graduation date: 1/2016
Ph.D.
Jia Zhan, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2016
Ph.D.
Ping Chi, Ph.D. in Computer Science and Engineering, expected graduation date: 6/2016
Ph.D.
Teaching
Course Course Evaluation
Semester
CSE 597A Modern VLSI Design 6.29 out of 7
Fall 2003
CSE 598C Reliable and Low Power Design 6.13 out of 7
Fall 2003
CSE 477 VLSI Digital Circuits 5.50 out of 7
Spring 2004
CSE 578 CAD Tools 5.91 out of 7
Fall 2004
CSE 477 VLSI Digital Circuits 5.17 out of 7
Spring 2005
CSE 578 CAD Tools 6.78 out of 7
Fall 2005
CSE 331.1 Computer Organization and Design 5.54 out of 7
Spring 2006
CSE 331.2 Computer Organization and Design 6.11 out of 7
Spring 2006
CSE 578 CAD Tools 5.88 out of 7
Fall 2006
CSE 431 Introduction to Computer Architecture 6.31 out of 7
Fall 2006
CSE 477 VLSI Digital Circuits 6.53 out of 7
Spring 2007
CSE 578 CAD Tools 6.53 out of 7
Fall 2008
CSE 411 VLSI Digital Circuits
Contact this candidate