Data Power

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February 01, 2013

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Journal of Circuits, Systems, and Computers

Vol. 20, No. 1 (2011) 125 145

# World Scienti c Publishing Company

DOI: 10.1142/S0218126611007116

NOISE-AWARE DATA PRESERVING SEQUENTIAL

MTCMOS CIRCUITS WITH DYNAMIC

FORWARD BODY BIAS

HAILONG JIAO* and VOLKAN KURSUNy

Department of Electronic and Computer Engineering,

The Hong Kong University of Science and Technology,

Clear Water Bay, Kowloon, Hong Kong

*******@***.**

*********@***.**

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for

suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential

MTCMOS circuit transitions from the sleep mode to the active mode, signi cant bouncing noise

is produced on the power and ground distribution networks. The reliability of the surrounding

active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this

paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacri cing

the data retention capability. With the new dynamic forward body bias technique, the peak

ground bouncing noise is reduced by up to 91.70% as compared to the previously published

sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeo s among

important design metrics such as ground bouncing noise, leakage power consumption, active

power consumption, data stability, and area are evaluated.

Keywords: Power gating; ground bouncing noise; data retention; tri-mode; threshold voltage

tuning; leakage power consumption; ip- op; shift register.

1. Introduction

The subthreshold leakage currents currently dominate the overall power consump-

tion of state-of-the-art integrated circuits due to the aggressive scaling of CMOS

technology over the years.1 One of the commonly used subthreshold leakage power

reduction strategies is MTCMOS (also known as power gating).2 In an MTCMOS

circuit, high threshold voltage (high-jVth j) sleep transistors (header and footer) are

used to cut o the power supply and/or the ground connection to the idle low

threshold voltage (low-jVth j) circuit blocks as shown in Fig. 1. Specialized MTCMOS

circuit techniques exist to maintain the data while lowering the leakage power

consumption in idle sequential circuits.2 4,6,10,12

125

126 H. Jiao & V. Kursun

VDD

L Bouncing Noise

Bouncing Noise

Real VDD Real VDD

SLEEP3

SLEEP 2 Header2 SLEEP1 Header3

Header1

Virtual VDD1

Virtual VDD2 Virtual VDD3

Already Active Awakening Already Active

... ...

MTCMOS MTCMOS MTCMOS

Sequential Circuit Sequential Circuit Combinational Circuit

Virtual GND 2 Virtual GND 1 Virtual GND 3

SLEEP 2 SLEEP 1 Footer 1 SLEEP 3 Footer 3

Footer 2

Real GND Real GND

Bouncing Noise Bouncing Noise

Fig. 1. A conventional multi-domain MTCMOS circuit with multiple autonomous low-jVth j circuit blocks

with individual distributed sleep transistors. High-jVth j sleep transistors are represented with a thick line in

the channel region. SLEEP1 : 0 ! VDD . SLEEP2 SLEEP3 VDD .

Data reliability is an important concern in sequential MTCMOS circuits. When a

typical sequential MTCMOS circuit transitions from the idle mode to the active

mode, high instantaneous currents ow through the sleep transistors. Large voltage

uctuations occur on both the real power line (power bouncing noise) and the real

ground distribution network (ground bouncing noise) as illustrated in Fig. 1. Bouncing

noise generated in one power-gating domain during a wake-up event is transferred

through the shared power and ground distribution networks to the surrounding active

circuit blocks.11 The node voltages and logic states of the active circuit blocks are

thereby disturbed in a multi-domain MTCMOS circuit. The ground bouncing noise is

expected to become an increasingly important reliability issue in future deeply scaled

multi-domain MTCMOS integrated circuits with shrinking noise margins.11 The

development of novel noise-aware sequential MTCMOS circuits with low leakage data

retention sleep mode capability is highly desirable.

In this paper, di erent sequential MTCMOS circuits with data retention capability

are evaluated. A new dynamic forward body bias technique is explored to signi cantly

suppress the ground bouncing noise produced by a sequential MTCMOS circuit

during the sleep to active mode transitions. The attractive application space of

di erent data preserving sequential MTCMOS circuit techniques is identi ed with a

rigorous characterization of various important design metrics.

The paper is organized as follows. Previously published sequential MTCMOS cir-

cuit techniques with data retention capability are described in Sec. 2. The new dynamic

forward body bias technique is introduced in Sec. 3 to reduce the ground bouncing

noise produced during sleep to active mode transitions. Post-layout simulation results

are presented in Sec. 4 to characterize the di erent data preserving sequential

MTCMOS circuit techniques. Finally, the paper is concluded in Sec. 5.

Noise-Aware Data Preserving Sequential MTCMOS Circuits 127

2. Previously Published Data Retention MTCMOS Flip-Flops

Various specialized power gating techniques are published in the literature to

maintain the data while reducing the leakage power consumption in idle sequential

MTCMOS circuits.2 4,6,10,12 These previously published sequential power gating

techniques are reviewed in this section. The conventional Mutoh MTCMOS ip- op

is discussed in Sec. 2.1. The Balloon MTCMOS ip- op is presented in Sec. 2.2. The

standard zero-body-biased tri-mode MTCMOS ip- op speci cally targeting the

ground bouncing noise issues in sequential MTCMOS circuits is described in Sec. 2.3.

2.1. Conventional Mutoh MTCMOS ip- op

The Mutoh ip- op (Mutoh-FF)2,3 is the rst-ever published MTCMOS FF with

data retention capability. The circuit schematic is shown in Fig. 2. The Mutoh-FF

provides a low-leakage sleep mode where the data is maintained in the master latch.

Distributed and localized header and footer sleep transistors are utilized in the

master and slave latches to eliminate the sneak leakage current paths. All of the

devices along the critical path of the Mutoh-FF have low jVth j for maintaining similar

Clock-to-Q speed as compared to a standard single low-jVth j FF. Although the

Mutoh-FF is capable of maintaining the data while lowering the leakage power

consumption, the circuit su ers from high area and active power consumption

overheads as compared to the standard single low-jVth j FF.22 Despite the signi cant

area and active power overheads, Mutoh-FF has been widely used and referenced as

an e ective technique to lower leakage currents in idle sequential MTCMOS

circuits.2,3,8,10 The noise characteristics of the Mutoh-FF however have been over-

looked and neglected until now. One of the important goals of this study is to

evaluate the signi cance of the ground bouncing noise produced by the Mutoh-FF

during the sleep to active mode transitions. As quantitatively shown in the following

Inv1

0.29/0.12

VDD

W = 6.0 W = 6.0

SLEEP

Header1 Header2

CLK

SLEEP

CLK

0.40/0.40 0.40/0.40

Node1 Node2 Node3

0.68/0.26 0.68/0.26

VDD SLEEP

CLK

SLEEP Footer1 Footer2

CLK W = 0.12

W = 3.6 W = 3.6

0.12/0.12

CLK

0.29/0.12 CLK

W = 0.12

CLK

Inv2

0.12/0.12

Fig. 2. The conventional MTCMOS ip- op (Mutoh-FF) with data preserving sleep mode.2,3 High-jVth j

transistors are represented with a thick line in the channel region. The transistor sizes (WPMOS =WNMOS are

in micrometers assuming an 80 nm CMOS technology. All the channel lengths are minimum (L 80 nm).

128 H. Jiao & V. Kursun

sections, the commonly cited Mutoh-FF su ers from high ground bouncing noise,

thereby seriously degrading the reliability of the surrounding active circuitry during

the reactivation events.

2.2. Balloon MTCMOS ip- op

An alternative MTCMOS ip- op (Balloon-FF) for providing a high speed and low

leakage data preserving sleep mode is presented in Ref. 4. A high-jVth j data retention

cell (Balloon) is attached to the slave latch of the Balloon-FF as shown in Fig. 3. All

of the devices on the forward and feedback paths have low jVth j. The Clock-to-Q

speed of the Balloon-FF is therefore similar to a standard single low-jVth j FF. A

centralized NMOS sleep switch is employed for cutting the ground connection of the

low-jVth j master and slave stages in the sleep mode with the Balloon-FF. Since only

one centralized NMOS sleep transistor is employed, the circuit area and active power

consumption overheads of Balloon-FF are reduced as compared to the Mutoh-FF.

The Balloon-FF, however, requires two extra control signals B1 and B2. Further-

more, these two control signals have complex timing requirements for storing and

retrieving the circuit state to and from the data retention balloon while entering and

0.29/0.12

Inv2

Inv1

0.12/0.12

Balloon 0.29/0.12

B2 B2

TGballoon

0.12/0.12

B1 B1

TGpass

CLK CLK

0.40/0.40 0.58/0.26 0.40/0.40 0.62/0.28

Node3

CLK CLK

0.12/0.12 0.12/0.12

0.12/0.12

0.31/0.12 0.31/0.12

Virtual Ground

SLEEP W = 1.1

Gated-Ground MTCMOS

Fig. 3. Low-leakage Balloon MTCMOS ip- op (Balloon-FF) with data preserving sleep mode.4 High-

jVth j transistors are represented with a thick line in the channel region. The transistor sizes

(WPMOS =WNMOS are in micrometers assuming an 80 nm CMOS technology. All the channel lengths are

minimum (L 80 nm).

Noise-Aware Data Preserving Sequential MTCMOS Circuits 129

leaving the sleep mode, respectively.12,22 The Balloon-FF has a high energy overhead

due to the complex data storage and recovery operations required for mode tran-

sitions. Furthermore, as quantitatively shown in the following sections, the Balloon-

FF produces high ground bouncing noise due to the high voltage swing on the virtual

ground line during the sleep to active mode transitions. The Balloon-FF thereby acts

as an aggressor that imposes a potential reliability problem for the surrounding

already active circuit blocks (see Fig. 1).

2.3. Standard tri-mode MTCMOS ip- op

A specialized tri-mode power gating structure is proposed in Ref. 6 to lower the

ground bouncing noise produced during the activation of idle MTCMOS circuits. All

of the devices on the forward and feedback paths of a tri-mode FF have low jVth j as

shown in Fig. 4. A high-jVth j PMOS data preserving transistor (Parker) is connected

in parallel with the footer (N1 to implement a low-leakage data retention sleep mode.

The Parker is activated while N1 is maintained cut-o (SLEEP PARK 0 V)

during the sleep mode. The virtual ground line is maintained at the threshold voltage

of the Parker (jVtp j). The circuit is capable of lowering the leakage power consumption

while retaining the data by maintaining a reduced yet signi cant voltage di erence

(VDD jVtp j between the power supply and the virtual ground line in the sleep mode.

Since there are no extra data retention elements attached to the forward path, the

parasitic capacitance on the critical path is smaller as compared to the Mutoh-FF and

Balloon-FF. The Clock-to-Q speed of the tri-mode FF is therefore faster as compared

to the Mutoh-FF and Balloon-FF.

VDD

CLK CLK

0.24/0.24 0.58/0.24 0.24/0.24 0.52/0.28

Inv1

CLK CLK CLK

CLK

Inv2

0.12/0.12 0.12/0.12

0.31/0.12 0.31/0.12

Virtual Ground

N1 PARK

SLEEP W: Optimization Parameter

W = 1.2

Fig. 4. Standard tri-mode MTCMOS ip- op with zero-body-biased high-jVth j Parker (TMH).6 High-jVth j

transistors are represented with a thick line in the channel region. The transistor sizes (WPMOS =WNMOS ) are

in micrometers assuming an 80 nm CMOS technology. All the channel lengths are minimum (L 80 nm).

130 H. Jiao & V. Kursun

A small-sized centralized footer (N1 ) is used with the tri-mode circuit. The current

produced by the smaller footer is reduced, thereby lowering the ground bouncing noise

produced during the transitions from the data retention sleep mode to the active mode

as compared to the Mutoh-FF. The ground bouncing noise produced by the tri-mode

circuit is also suppressed due to the lower range of the voltage swing on the virtual

ground line during the reactivation events as compared to the Balloon-FF.

In addition to o ering a low-leakage data retention sleep mode, the tri-mode

technique also provides an optional minimum leakage deep sleep mode.10 When the

data in idle sequential MTCMOS circuits are not required to be maintained, the tri-

mode FF can transition to the alternative minimum leakage deep sleep mode

(SLEEP 0 and PARK VDD ) where the data are lost.10 Leakage savings are

maximized by turning o the footer and the Parker in the deep sleep mode at the cost

of losing the pre-sleep circuit state. In this paper, sleep mode data retention is assumed

to be required in the sequential MTCMOS circuits. Therefore, the optional deep sleep

mode provided by the tri-mode technique is not utilized in the following sections.

3. The New Dynamic-Forward-Body-Biased Tri-Mode

MTCMOS Flip-Flop

A new design strategy based on threshold voltage tuning is described in this section

to further suppress the ground bouncing noise produced during transitions from data

retention sleep mode to active mode in sequential MTCMOS circuits. A dynamic-

forward-body-biased noise-aware tri-mode MTCMOS circuit technique is proposed

as shown in Fig. 5.

The high-jVth j Parker in the standard tri-mode circuit is substituted by a low-jVth j

Parker as shown in Fig. 5(a). The threshold voltage of the Parker is further reduced

by applying forward body bias. The steady-state sleep mode voltage on the virtual

ground line of the tri-mode circuit with a forward-body-biased low-jVth j Parker is

decreased, thereby reducing the voltage swing on the virtual ground line during the

sleep to active mode transition as compared to the standard zero-body-biased tri-

mode circuit. When the footer is turned on to resume the high performance active

mode operations of the tri-mode circuit, the peak ground bouncing noise is sup-

pressed with the proposed forward body bias technique. Furthermore, the data

stability is enhanced by lowering the steady-state voltage of the virtual ground line in

the sleep mode.

The previously published conventional forward body bias techniques14 16 cannot

be directly applied to the Parker since the virtual ground line voltage (the source of

the Parker is attached to the virtual ground line) varies with the mode of operation of

an MTCMOS circuit, the size of the Parker, and the size of the low-jVth j circuit block.

A new forward body bias generator is therefore proposed in this paper. The circuit is

shown in Fig. 5(b). A low-jVth j NMOS transistor (Biaser) and a negative DC voltage

source (Vbias are attached to the tri-mode circuit to produce a dynamically adjusted

Noise-Aware Data Preserving Sequential MTCMOS Circuits 131

VDD

CLK CLK

0.24/0.24 0.58/0.24 0.24/0.24 0.52/0.28

Inv1 D1

Isub

CLK CLK D2

CLK Parker

CLK

Biaser D3

Inv2

0.12/0.12 0.12/0.12

0.31/0.12 0.31/0.12

Virtual Ground

Vbias

PARK

SLEEP Biaser

W = 1.2

W = 0.12 W: Optimization

Parameter

Vbias

(a) (b)

Fig. 5. Proposed sequential MTCMOS circuit with dynamic-forward-body-biased Parker (DFBB).

(a) The tri-mode MTCMOS ip- op with a dynamic-forward-body-biased low-jVth j Parker (DFBBL).

(b) The proposed dynamic forward body bias generator for the Parker. High-jVth j transistors are rep-

resented with a thick line in the channel region. The transistor sizes (WPMOS =WNMOS ) are in micrometers

assuming an 80 nm CMOS technology. All the channel lengths are minimum (L 80 nm).

body voltage for the Parker. The Biaser is maintained cut-o by shorting the gate

and the source terminals. The drain current of the Biaser controls the body current of

the Parker. The body current of the Parker is primarily composed of the currents

produced by D1 (I1 and D2 (I2 as illustrated in Fig. 5(b). D1 and D2 are the source-

to-body and drain-to-body p n junctions, respectively, of the Parker.

During the sleep mode, the virtual ground line is charged to jVtp j. The body of the

Parker is maintained at a voltage level between jVtp j and Vbias . D1 is forward biased.

During the subsequent active mode, the virtual ground line is discharged to $ Vgnd .

The body of the Parker is maintained at a voltage level between Vgnd and Vbias . Both

D1 and D2 are forward biased. The Parker thereby experiences continuous forward

body bias in both sleep and active modes with the proposed technique.

The subthreshold leakage current (Isub produced by the Biaser and the body

voltage of the Parker are determined by Vbias . Isub is

Isub I1 I2 : 1

The body voltage of the Parker is dynamically adjusted by the body bias generator to

satisfy Eq. (1) during the di erent modes of operation. The forward body bias vol-

tage of the Parker is tuned by adjusting Vbias . Higher Isub enhances the forward body

bias voltage experienced by the Parker, thereby lowering the ground bouncing noise

as well as strengthening the data stability. Higher Isub, however, also increases the

132 H. Jiao & V. Kursun

leakage power consumption in the sleep mode. The leakage power consumption of the

tri-mode circuit can be restricted to an acceptably low level by choosing an appro-

priate Vbias as further discussed in the following sections.

4. Simulation Results

The UMC 80 nm multi-threshold voltage CMOS technology17 (high-Vth NMOS 370 mV,

low-Vth NMOS 155 mV, high-Vth PMOS 310 mV, low-Vth PMOS 105 mV,

and VDD 1 V) is used in this paper for the characterization of ground bouncing noise,

leakage power consumption, active power consumption, data stability, and area

overheads with the di erent sequential MTCMOS techniques. Five 32-bit shift regis-

ters are designed based on the following techniques: standard single low-jVth j FF,

the conventional Mutoh-FF (Fig. 2), the Balloon-FF (Fig. 3), the standard zero-body-

biased tri-mode technique (TMH in Fig. 4), and the dynamic-forward-body-biased

tri-mode technique (DFBBL in Fig. 5). All the data presented in this section are

produced by post-layout simulation with Synopsys HSPICE.19 The layouts are drawn

with Cadence Virtuoso.20 2D parasitic RC extraction of the layouts is performed with

Cadence Assura.21

The design criterion used in this paper for the sizing of sleep transistors is to

achieve similar propagation delays (within 5%) with each ip- op and shift register.

The load and the driver used for propagation delay measurements are identical ip-

ops (for example, a standard single low-jVth j ip- op driving an identical standard

single low-jVth j ip- op or a TMH ip- op driving an identical TMH ip- op). The

input data slew and clock slew are 50 ps for each ip- op. The low-jVth j circuitry of

each FF is carefully sized to achieve similar output rise and fall times as well as

similar high-to-low and low-to-high propagation delays. The low-jVth j segments of

the Mutoh-FF and Balloon-FF are also sized larger (in addition to appropriate sleep

transistor sizing) to meet the timing requirement as compared to the standard single

low-jVth j FF. The sizes of di erent MTCMOS FFs to satisfy the timing criterion with

this UMC 80 nm CMOS technology are shown in Figs. 2 5. The sizes of sleep

transistors used with di erent MTCMOS FFs and MTCMOS shift registers are listed

in Table 1. The mutually exclusive switching patterns (the data in the adjacent ip-

ops of the shift registers never switch in the same direction) are exploited to further

reduce the sizes of the sleep transistors in the Balloon, TMH, and DFBBL shift

Table 1. The sizes of sleep transistors with di erent techniques.

Flip- op Shift register

Header ( m) Footer ( m) Header ( m) Footer ( m)

Circuit technique

Mutoh 12.0 7.2 384.0 230.4

Balloon N/A 1.1 N/A 17.6

TMH N/A 1.2 N/A 19.2

DFBBL N/A 1.2 N/A 19.2

Noise-Aware Data Preserving Sequential MTCMOS Circuits 133

registers.7 Alternatively, sleep transistors of di erent FFs in the Mutoh shift register

cannot be shared. Localized and distributed sleep transistors are required in order to

eliminate the sneak leakage current paths in Mutoh-FF.22 Di erent tapered bu er

chains are employed to provide similar signal rise and fall times to the sleep tran-

sistors and the clock distribution network with each technique.

Section 4 is organized as follows. The ground bouncing noise produced by di erent

sequential MTCMOS circuits during the sleep to active mode transitions is evaluated

in Sec. 4.1. The leakage power consumed by di erent shift registers is compared in

Sec. 4.2. The active power consumption of the shift registers are presented in Sec. 4.3.

The area overheads of the MTCMOS shift registers are compared in Sec. 4.4. The

data stabilities of the MTCMOS FFs in the sleep mode are evaluated in Sec. 4.5. A

comprehensive design metric is proposed in Sec. 4.6 to compare the overall electrical

quality of data preserving sequential MTCMOS shift registers.

4.1. Ground bouncing noise

The ground bouncing noise produced by the sequential MTCMOS circuits is

characterized in this section. The commonly used and well characterized 40-pin Dual

In-line Package (DIP-40) model is used in this paper to evaluate the ground bouncing

noise phenomenon in sequential MTCMOS circuits. The parasitic resistance,

inductance, and capacitance of the DIP-40 are 217 m, 8.18 nH, and 5.32 pF,

respectively.5,10,12,18

In order to evaluate the tradeo s between ground bouncing noise and leakage

power consumption with the TMH and DFBBL techniques, the width of the Parker is

varied from the minimum size allowed by the technology (0.12 m) to 15 m. Fur-

thermore, Vbias in the DFBBL circuit is swept from 0 V to 700 mV to evaluate the

dependence of ground bouncing noise on the value of Vbias . When Vbias 0 V, the gate

and source of the Biaser are directly connected to the ground. The additional voltage

reference within the body bias generator is thereby eliminated. While the Parker is

forward-body-biased even with Vbias 0 V, to be able to produce higher forward body

bias voltages that can further reduce the ground bouncing noise while enhancing the

data stability with di erent Parker sizes, an additional nonzero voltage reference

(Vbias ) is required with the proposed body bias generator. The nonzero voltage refer-

ence Vbias, however, requires additional design e ort and causes area overhead. The

minimum applicable Vbias is assumed to be 700 mV15,16 in this study to maintain the

reliability of the Biaser (to avoid strong forward currents through the body diodes).

The Biaser is sized minimum (0.12 m) to lower the area overhead. The ground

bouncing noise produced with di erent tri-mode circuits are shown in Figs. 6 and 7.

When the size of the Parker increases, the steady-state sleep-mode voltage of the

virtual ground line with the tri-mode circuit decreases. The voltage swing on the

virtual ground line is therefore reduced during the transition from the sleep mode to

the active mode. The peak ground bouncing noise produced by di erent tri-mode

134 H. Jiao & V. Kursun

Peak Amplitude of Ground Bouncing Noise (mV)

TMH

TMH 23

DFBBL (Vbias = 0mV)

DFBBL (Vbias = 0mV) 22

DFBBL (Vbias = -700mV)

DFBBL (Vbias = -700mV) 21

14 14

13 13

12 12

11 11

0 1 2 3 4 5 6 7 8 *-**-**-**-**-** 15 0 1 2 3 4 5 6 7 8 *-**-**-**-**-** 15

Parker Size ( m) Parker Size ( m)

(a) (b)

Fig. 6. The peak ground bouncing noise produced by the TMH and DFBBL shift registers with di erent

Parker sizes. T 90 C. (a) Stored data \0". (b) Stored data \1". The minimum Parker size on the X

axis is 0.12 m.

Peak Amplitude of Ground Bouncing Noise (mV)

21 22

Parker = 0.12 m Parker = 0.12 m

Parker = 15 m Parker = 15 m

13 13

12 12

11 11

0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7

Vbias (V) Vbias (V)

(a) (b)

Fig. 7. The peak ground bouncing noise produced by the DFBBL shift register at di erent Vbias .

T 90 C. (a) Stored data \0". (b) Stored data \1".

circuits during the reactivation events thereby monotonically decreases with the

increased Parker size as shown in Fig. 6.

Isub (in Eq. (1)) is increased when Vbias is decreased from 0 mV to 700 mV, thereby

enhancing the forward body bias voltage experienced by the Parker in the DFBBL

circuit. The threshold voltage of the Parker is therefore reduced with the decreased

Vbias . The peak ground bouncing noise produced by the DFBBL circuit monotonically

decreases with the reduced Vbias due to the suppressed voltage swing on the virtual

ground line during the sleep to active mode transition as shown in Fig. 7.

The peak amplitudes of the ground bouncing noise induced on the real ground

distribution network with di erent MTCMOS circuit techniques are listed in Table 2.

Noise-Aware Data Preserving Sequential MTCMOS Circuits 135

Table 2. Peak amplitudes (mV) of ground bouncing

noise with di erent MTCMOS techniques.

Circuit technique Stored data: 0 Stored data: 1

Mutoh 135.47 134.74

Balloon 66.97 60.69

16.01 22.13 17.05 23.55

TMH

11.25 19.95 11.83 21.31

DFBBL

Stored data = 1

Stored data = 0

Stored data = 0 Parker Size = 0.12 m (Vbias = 0mV with DFBBL)

Stored data = 0 Parker Size = 15 m (Vbias = -700mV with DFBBL)

Stored data = 1 Parker Size = 0.12 m (Vbias = 0mV with DFBBL)

Stored data = 1 Parker Size = 15 m (Vbias = -700mV with DFBBL)

95%

Percent Reduction of Ground Bouncing Noise

85%

75%

65%

55%

45%

Balloon TMH DFBBL

Fig. 8. Percent reduction of ground bouncing noise produced with di erent MTCMOS circuit techniques

as compared to the conventional Mutoh technique at 90 C.

The percent reductions of ground bouncing noise produced with di erent circuit

techniques as compared to the Mutoh shift register are shown in Fig. 8. The simulation

temperature is 90 C. The Mutoh shift register is used as a worst-case reference since

the highest ground bouncing noise is produced by the Mutoh shift register among the

sequential MTCMOS circuits evaluated in this paper. The total size of the sleep

transistors is signi cantly larger in the Mutoh shift register as compared to the other

MTCMOS circuit techniques. The Mutoh shift register therefore produces higher

instantaneous currents and more signi cant noise during the transitions from the

sleep mode to the active mode.

The DFBBL shift register achieves the lowest ground bouncing noise among the

MTCMOS techniques evaluated in this paper due to the suppressed voltage swing on

the virtual ground line with the proposed threshold voltage tuning strategy. The

peak ground bouncing noise is reduced by up to 91.70% and 83.20% as compared to

136 H. Jiao & V. Kursun

the Mutoh and Balloon shift registers, respectively. Furthermore, the DFBBL shift

TMH shift register with the same Parker size.

4.2. Leakage power consumption

The leakage power consumption of the 32-bit shift registers designed with di erent

circuit techniques are evaluated in this section. The majority of the MTCMOS

circuits evaluated in this paper utilize the modi ed gated-ground technique. The

virtual ground and the internal nodes of a gated-ground MTCMOS circuit have high

steady-state voltages in the low leakage data retention sleep mode. A high data input

(D VDD is therefore assumed for the leakage power measurements. The data

stored in each ip- op of the shift registers are assumed to be the same (either all \0"

or all \1"). The leakage power consumption with the TMH and DFBBL shift reg-

isters are shown in Figs. 9 and 10. The simulation temperature is 90 C.

The Parkers in the TMH and DFBBL shift registers are turned on to maintain a

reduced yet signi cant voltage di erence between the power and ground connections

of the low-jVth j sequential circuits in the data retention sleep mode. The leakage

power consumed by the TMH and DFBBL shift registers are therefore determined by

the e ective supply voltage experienced by the low-jVth j sequential circuits and the

size of the Parker. When the size of the Parker is increased, the steady-state sleep-

mode voltage of the virtual ground line is reduced, thereby enhancing the e ective

supply voltage experienced by the low-jVth j sequential circuits. Higher drain current

is produced by the active Parker, thereby increasing the leakage power consumption

in the sleep mode as shown in Fig. 9.

The steady-state sleep-mode voltage of the virtual ground line is reduced with the

decreased Vbias in the DFBBL shift register as discussed in Sec. 4.1. The e ective

Leakage Power Consumption ( W)

DFBBL (Vbias = -700mV)

DFBBL (Vbias = 0mV)

TMH

3 TMH

0 1 2 3 4 5 6 7 8 *-**-**-**-**-** 15

Parker Size ( m)

(a) (b)

Fig. 9. The leakage power consumed by the TMH and DFBBL shift registers with di erent Parker sizes.

T 90 C. (a) Stored data \0". (b) Stored data \1". The minimum Parker size on the X axis

is 0.12 m.

Noise-Aware Data Preserving Sequential MTCMOS Circuits 137

Leakage Power Consumption ( W)

Parker = 15 m

Parker = 0.12 m

Parker = 0.12 m 5

0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7

Vbias (V)

(a) (b)

Fig. 10. The leakage power consumed by the DFBBL shift register at di erent Vbias . T 90 C. (a) Stored

data \0". (b) Stored data \1".

supply voltage experienced by the low-jVth j sequential circuits is thereby enhanced.

Furthermore, the body diode currents of the Parker and Biaser are increased as Vbias

is reduced. The leakage power consumption of the DFBBL shift register therefore

monotonically increases with decreased Vbias as shown in Fig. 10.

The leakage power consumed by di erent shift registers is listed in Table 3. The

percent leakage power reductions provided by di erent MTCMOS circuit techniques

in the data retention sleep mode (as compared to the standard single low-jVth j shift

sumes the highest leakage power (among MTCMOS circuits) due to the highest drain

current through the active Parker and the high body diode currents of the Parker and

the body bias generator. The DFBBL shift register increases the leakage power con-

sumption by 3:16 to 7:57 and 7:26 to 16:25 as compared to the Mutoh and

Balloon shift registers, respectively, depending on the stored data, the size of the

Parker, and the value of Vbias . Furthermore, the DFBBL shift register increases the

Leakage power consumption ( W) of di erent shift registers.

Table 3.

Circuit technique Stored data: 0 Stored data: 1

Standard single low-jVth j 15.468 15.616

Mutoh 1.073 0.940

Balloon 0.468 0.438

2.842 4.897 2.767 4.722

TMH

3.396 7.401 3.300 7.116

DFBBL

Note: The minimum and the maximum leakage power consumption with

the TMH circuit are observed when the Parker size is 0.12 m and 15 m,

respectively. The minimum and the maximum leakage power consump-

tion with the DFBBL circuit are observed when the Parker size is 0.12 m

with Vbias 0 mV and the Parker size is 15 m with Vbias 700 mV,

respectively.

138 H. Jiao & V. Kursun

Stored data = 1

Stored data = 0

Stored data = 0 Parker Size = 0.12 m (Vbias = 0mV with DFBBL)

Stored data = 0 Parker Size = 15 m (Vbias = -700mV with DFBBL)

Stored data = 1 Parker Size = 0.12 m (Vbias = 0mV with DFBBL)

Stored data = 1 Parker Size = 15 m (Vbias = -700mV with DFBBL)

100%

Percent Leakage Power Reduction

90%

80%

70%

60%

50%

Mutoh Balloon TMH DFBBL

Fig. 11. Percent leakage power reduction provided by di erent MTCMOS circuit techniques in the sleep

mode as compared to the standard single low-jVth j shift register.

leakage power consumption by up to 1:65 as compared to the TMH shift register with

the same Parker size. However, as compared to the standard single low-jVth j shift

by 52.15% 78.87% as shown in Fig. 11. The DFBBL technique thereby maintains the

e ectiveness in suppressing the leakage power consumption as compared to the stan-

dard single low-jVth j shift register in the sleep mode.

Alternatively, the Balloon shift register consumes the lowest leakage power

among the MTCMOS shift registers evaluated in this paper. As listed in Table 3, the

Balloon shift register reduces the leakage power consumption by up to 97.20%,

93.84%, 90.72%, and 56.38% as compared to the standard single low-jVth j, DFBBL,

TMH, and Mutoh shift registers, respectively.

4.3. Active power consumption

The active power consumption with di erent shift registers is evaluated in this

section. The clock frequency is 2 GHz. The simulation temperature is 90 C. The

active power consumed by di erent shift registers is listed in Table 4. The normalized

(with respect to the active power consumed by the Mutoh shift register) active power

consumption with di erent circuit techniques are shown in Fig. 12.

The Mutoh-FF and Balloon-FF employ additional transistors and circuitry for

implementing a low leakage data retention sleep mode. Furthermore, for similar

speed, the transistors in the Mutoh-FF and Balloon-FF are sized larger as compared

Noise-Aware Data Preserving Sequential MTCMOS Circuits 139

Table 4. Active power consumption (mW)

of di erent shift registers.

Circuit technique Active power

Standard single low-jVth j 1.624

Mutoh 3.062

Balloon 2.509

TMH 1.314

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