Swathi T. Gurumani

**** ***** ***** *****, 256-***-**** (M)

Huntsville, AL 35806 E-mail: abqgpr@r.postjobfree.com

Web: www.ece.uah.edu/~gurumas

OBJECTIVE

To obtain a position in a research and development environment that can utilize both my professional and

educational background relating to computer engineering.

PROFILE

Expertise and hands-on experience in reconfigurable computing, FPGAs and related tools

Experience in hardware design and parallel programming

Sound background in computer architecture and hardware/software co-design principles

2+ years of professional work experience in development and research environment

4+ years of lecturing and teaching experience

Honest and hard-working, motivated team player

EDUCATION

Ph. D. in Computer Engineering, University of Alabama in Huntsville, AL, August 2007. GPA: 3.88

Dissertation: Energy-Efficient Dynamic Task Scheduler for Reconfigurable System-on-Chip Architectures

Graduated as Outstanding Graduate Student of ECE Department, 2006.

Master of Science in Computer Engineering, University of Alabama in Huntsville, AL, 2003. GPA: 3.88

Thesis: An Intellectual Property Core to Support Communicating Sequential Processes

Bachelor of Engineering in Electronics and Communications Engineering, Madras University, India, 2000.

KEY SKILLS

Hardware Modeling: VHDL RTL coding, synthesis and simulation, Verilog, VIVA (Starbridge

systems), SystemVerilog

Hardware Design Tools: Xilinx ISE, Altera Quartus/Maxplus, Leonardo, ModelSim, Synopsis

Hardware/Software Codesign: Xilinx Microblaze Soft Processor, SystemC, HandelC

Programming Languages: C/C++, Assembly, FORTRAN, PERL, HTML

Parallel Programming: PVM/MPI, POSIX thread

Embedded System: Assembly, C, MIPS, Intel 80x86, ARM

Design Tools/Test Equipment: Logic Analyzer, Emulator, Oscilloscope, Device Programmer

Software Tools: Gnu C, MathLab, Simulink, Electronics Workbench, MS Office Suite

Operating System: Windows XP, Unix, Sun Solaris, Linux (Ubuntu)

Processor Performance Simulation Tools: SimpleScalar, PowerAnalyzer

PROFESSIONAL EXPERIENCE

Senior Research Associate Feb. 04 July 04

ECE Department, University of Alabama in Huntsville, AL.

Responsibilities include researching and presenting techniques for implementing optimization

techniques in reconfigurable hardware.

Researched and presented on the existing techniques for automatic generation of hardware from high-

level languages (high-level synthesis techniques)

Software Programmer Sep 00 Jul 01

Kumaran Systems Inc., Chennai, India - Data Warehousing Division.

Involved in the design, development and testing of Data Marts

Responsibilities include study and cleansing of existing data (OLTP systems), design and

development of Data Models, design and loading of data into target database (OLAP system)

Swathi T. Gurumani

OTHER EXPERIENCE

Graduate Teaching Assistant Aug. 01-Aug. 07

ECE Department, University of Alabama in Huntsville, AL.

Lecturer for a senior level undergraduate course (Introduction to Computer Architecture).

Lab instructor for Data Structures in C++, Advanced Logic Design (Graduate/Senior level course),

Electronics Measurements Laboratory, Introduction to C++ programming

Graduate Research Assistant [Aug. 04 April 06]

Deployable Autonomous Distributed Sensor (DADS) Systems Program

Univ. of Alabama Huntsville Univ. of Alabama Birmingham collaborative Project

Implemented a coarse-grain parallel PSO algorithm with three different communication strategies

using MPI on a Beowulf cluster.

Developed analytical performance models to predict run-time behavior for various modifications of

parallel particle swarm optimization algorithms.

[Jan 02 Jun 02]

Created databases of facial images with OpenCV (Computer Vision Library) developed by Intel and

tested the library for accuracy of results.

Modified existing library to incorporate changes in the Face Recognition Software (HMMDemo) to be

used in real-time applications.

KEY PROJECTS

Designed and implemented a Laplacian spatial filter for real-time streaming video in Verilog using

Xilinx multimedia board. Test inputs were generated using SystemVerilog.

Designed and implemented a hardware/software co-design system for a game controller, which used

neural network algorithms. Xilinx FPGA with Microblaze soft processor was used in the co-design.

Compared and analyzed the simulation results of Space Shuttle Main Engine code by running it on

Microblaze soft processor using Xilinx FPGAs.

Implemented a fine-grained fully pipelined FPGA implementation of IDEA encryption algorithm

using VIVA GUI software. (Starbridge Systems)

Surveyed and reported on hardware support for tamper-evident/resistant processing and secure

processors.

Performed performance analysis and power estimation of ARM processor by executing MiBench

benchmark suite using Power Analyzer and SimpleScalar.

Performed performance and memory characterization of selected SPEC CPU2000 benchmarks using

Vtune Performance Analyzer

Implemented a parallel 2-D Poisson solver for Particle-in-Cell (PIC) code using Tri-diagonal Matrix

method in MPI FORTRAN.

Implemented MU0 a 16-bit RISC processor in VHDL.

Implemented a two-pass assembler in PERL for a newly designed CSP-like processor. The assembler

checked for proper instruction format and syntax during the first pass and checked for functionality

and logical errors in the second pass.

Designed and implemented a greedy algorithm in C language to solve the N-Queens problem by

placing it only on the boundary squares.

Developed a package in C language to count the number of chromosomes in a given medical image

using image enhancement techniques and increased the dynamic range of images.

PUBLICATIONS

Configuration-Aware Scheduling and Dynamic Power Management in RSoC Architectures,

Submitted to Eurasip Journal on Embedded systems (Under Review)

Swathi T. Gurumani

Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip

Architectures, Proceedings of International conference on Engineering of Reconfigurable Systems

and Algorithms, ERSA, Las Vegas, June 2007.

Dynamic Power Management in Power-Aware Reconfigurable System-on-Chip Architectures,

Proceedings of International conference on Embedded Systems and Applications, Las Vegas, June

2007.

Performance Analysis of Coarse-Grained Parallel Particle Swarm Optimization, Proceedings of 19th

International Conference on Parallel and Distributed Computing Systems, San Francisco, September

2006.

Execution Characteristics of SPEC CPU2000 Benchmarks: Intel C++ vs. Microsoft VC++,

Proceedings of 42nd Annual ACM Southeast Conference, Huntsville AL, April 2004.

Exploiting Fin-Grain Parallelism of IDEA Using Xilinx FPGA, Proceedings of 16th International

Conference on Parallel and Distributed Computing Systems, Reno-NV, August 2003.

PRESENTATIONS

Hardware implementation technique for Genetic Algorithms, UAH-UAB Teleconference.

Parallelization opportunities in Particle Swarm Optimization algorithm, UAH-UAB Teleconference.

Survey on current generation FPGA architectures, Reconfigurable Computing Lab, UAH.

Dynamic power management in RSoC Architectures, BBLT Research Talks Series, UAH.

Comparison of compilers: Intel C++ vs. Microsoft VC++, LaCASA lab (Laboratory for Advanced

Computer Architectures and Systems at Alabama)

Lecture series for Introduction to Computer Architecture course for a whole semester.

HONORS AND ACHIEVEMENTS

Awarded Outstanding Graduate Student of ECE Department, 2006.

Invited member of Phi Kappa Phi National academic honor society

Invited member of Eta Kappa Nu Electrical and Computer Engineering national honor society

Listed in Dean s List (Graduate School), Academic Year 2003, 2005, University of Alabama in Huntsville.

REFERENCES Available upon request.

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