Anil Kumar*-**, Overlea Crt, Kitchener, ON N*M *V*

Tel:519-***-****

E-mail:abqgph@r.postjobfree.com

URL:http://www.ece.uwaterloo.ca/~a3kumar

EducationCandidate for PhD Electrical Engineering

Jan. 01 present- University of Waterloo, Waterloo, Ontario

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Amorphous Silicon Devices & Integrated Circuit Group.

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OLED-display source-driver circuit.

B. Tech. In Electronics Engineering

Jul 1994 - May 1998 - Institute of Technology BHU Varanasi, India

-- Analog/Digital Circuits

Graduate CoursesMicroelectronic Processing Technology

Physics & Modeling of Semiconductor DevicesLarge Area ElectronicsSilicon on Insulator Devices & CircuitsAdvanced Digital Integrated CircuitsComputer Aided Design of CircuitsVLSI Quality & Reliability Engineering Work ExperienceMotorola Semiconductors India Limited (Circuit Design Engineer)--Sept. 1999 --- Dec 2000Duet Technologies India Limited (Circuit Design Engineer)--July 1998 --- Aug. 1999University of Waterloo,Research Assistant --Jan 01 - Present

--Amorphous Silicon Devices & Integrated Circuit Group

Teaching Assistant

--- ECE 439 Digital Circuit

--- ECE 209 Material Science

--- ECE 332 Electronic CircuitsPublications/Presentations

Anil Kumar, Peyman servati, Arokia Nathan

5-Transistor current based Amorphous silicon driver circuit for OLED display, CITO Knowledge conference, Ottawa,

Octo. 2001.

Kapil Sakariya, Peyman Servati, Anil Kumar, Arokia Nathan.

Amorphous silicon pixel driver circuits for mobile OLED displays, May 2002, SPIE Conference Ottawa, Canada.

K. Sakariya, P. Servati, A. Kumar, A. Nathan, Amorphous silicon

Pixel driver circuits for mobile OLED displays, Opto-Canada: SPIE Regional Meeting on Optoelectronics, Photonics and Imaging, SPIE vol. TD01, May 2002, pp. 390-392.

A. Nathan, K. Sakariya, A. Kumar, P. Servati, and D.

Striakhilev, Thin Film Driver Circuits for OLED Displays, Invited paper, Photonics 2002: 6th International Conference on

Optoelectronics, Fiber-optics and Photonics, Dec. 2002, p. 362.

A. Nathan, K. Sakariya, A. Kumar, K. S. Karim, D.

Striakhilev, Low temperature a-Si:H pixel circuits for mechanically flexible displays, abstract submitted and accepted for

MRS 2003 Spring meeting, April 2003.

A. Nathan, K. Sakariya, A. Kumar, P. Servati,

D. Striakhilev, Amorphous silicon back-plane electronics for OLED displays, Proceedings of the 15th Annual Meeting of the

IEEE Laser and Electro-Optics Society (LEOS), Nov. 2002.

A. Kumar, K. Sakariya, P. Servati, S. Alexander,

D. Striakhilev, K. S.Karim, A. Nathan, M. Hack Design considerations for active matrix organic light emitting diode

To appear (in IEE Journals).

Arokia Nathan, Kapil Sakariya, Anil Kumar, Peyman Servati,

Karim S. Karim, Denis Striakhilev, Andrei Sazonov Amorphous silicon TFT circuit integration for OLED displays on glass

and plastic. 2003 CICC conference (To appear).

Arokia Nathan, Anil Kumar, Kapil Sakariya, Peyman Servati,

Karim S. Karim, Denis Striakhilev, Andrei Sazonov Amorphous silicon backplane electronics for OLED displays Journal of

Quantum Electronics (To appear).Patent

A. Nathan, K. Karim, N. Mohan, A. Kumar, K. Sakariya,

Integrated multiplexer/de-multiplexer for active-matrix display/imaging arrays, patent pending (filed in Aug. 2002).

Projects DoneGraduate Projects16-bit Adder design in 0.18u CMOS technology at 3 GHz

frequency simulation, layout, layout-extraction and post layout simulation.1K SRAM memory design in SOS technology.Simulator design in MATLAB for simulation of elementary

electronic circuit.Industrial Projects1K SRAM Design for Patriot chip in HIP7 technology.

1K SRAM Design for Patriot Chip in HIP6 technology.

Synopsys: Earlier Patriot chip was using 0.25k Memory Modules. For

area saving purpose we designed 1k Module in HIP6W technology.

Responsibility : Generation of specifications based on Patriot full chip

guidelines. Schematic entry for critical path and LVS. Estimation of

load at critical nodes. Pre-layout simulation with these estimated loads.

Layout formation with DRC and LVS check. Parasitic extraction and

post-layout simulation.

I/O ring development for WHITECAP chip.

Synopsys : This I/O ring consisted of 167 I/O pads. These I/O's were

ESD compliant of 1.5KV HBM..Schimmit Trigger design was also done as a part of Clock Amplifier pad.

Responsibility : The design was existing in Motorola's HIP6W process

and it had to be ported to TSMC 0.18u. The basic challenge in terms of

effort was ESD circuit which was totally different.Here instead of

driver fingers being used as ESD path separate Diodes were provided

for ESD discharge. While TSMC supports Driver finger's being used as ESD discharge path where drain substrate junction diode breaks and

later on, turns on source substrate junction which triggers snapback and

grounds the spikes.

PLL Design layout and Post layout simulation.

Synopsys : The product consisted of PLL core and user programmable

divider. The PLL core was mixed signal block containing Phase Frequency Detector. Charge pump, Low Pass Filter, Voltage Controlled Oscillator, Forward and Feedback divider, Power on reset, Lock detector and Digital control block. It had two modes of operation, Transparent mode and PLL mode. It also had a synchronous

and asynchronous reset. VCO was basically a Current Controlled Oscillator (CCO) preceded by voltage to current converter. CCO was basically a ring oscillator with gain 1.73.

Responsibility: VCO design and Full custom layout formation and

verification.

HSTL ( High Speed Transceiver Logic) I/O buffer, a 1.5V output buffer

supply voltage based interface standard for digital integrated circui

Synopsys: As CMOS digital integrated circuits and systems is designed

to operate at higher frequency,considerable emphasis is being give

using I/O buffers that have low voltage swings above and be reference

voltage to indicate a logic High or logic Low, respectively. The

performance properties of such buffers make them attractive candidate

for high-speed application at frequencies above 100MHz.HSTL I/O

buffers belong to this category. They have a 1.5v supply voltage and are targeted at applications that require high speed data communication such as DSP, fast computing system. The basic HSTL I/O cell structure consists of a differential amplifier input with one input tied to a user supplied input reference voltage (Vref=0.75v) and an output buffer that uses a separate output supply voltage (1.5v) that is different from device supply voltage(VDD=3.3v).

Responsibility: Design and pre-layout simulation, Layout formation and verification parasitic extraction, post-layout simulation, and

characterization.

Undergraduate ProjectsBarrel Shifter design (8-Bit) using Viewlogic tools.

Design was captured in VHDL as RTL code,simulated and synthesized

using synthesis tools. Layout was done manually due to unavailability of

tools. Basic NAND gate was also fabricated in departmental foundry and

characterized too.

Thick film resistor design fabrication characterization.Realization of a computer game in C language using Graphics.Tools UsedMATLAB

HSPICE/PSPICE

PDRACULA DRC/LVS/LPE TOOLS

MCSPICE

CALIBRE/XCALICRE (DRC/LVS/LPE)

VIRTUOSO/LAYOUTPLUS

Awards/Achievements UGC ( University Grant Commission) Merit Scholarship, Institute

of Techonology BHU, Varanasi, India ( July 1994 May 1998).IIT (Indian Institute of Technology) JEE (Joint Entrance

Examination) All India Rank --- 855.Research Assistantship, University of Waterloo, (May 2001 Present).

International Graduate Student Scholarship, University of waterloo

(Jan 2001- Present).Graduate Performance Scholarship, University of Waterloo

(Sep 2001 Apr 2002).Teaching Assistantship, University of Waterloo, (May 2001- Present)

Activities Member of troubleshooting committee in cultural festival of Inst. Of

Technology BHU Varanasi, India.IEEE Student member.SID Student member.

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