abqfjc@r.postjobfree.com

Accomplishments

• Developed electroless nickel bath inhibitor to control a surface-loading phenomenon on semiconductor deposition processes. With standard inhibitors electroless nickel plating on wafers would not have been manufacturable.

• Lead development and implementation of tin-silver and tin-copper plating baths and compatible bus (seed) metal etchants for manufacture of lead-free semiconductor devices for Flip-Chip assembly. Freescale continues to use this lead-free plating process on its Flip -Chip wafers.

• Initiated development of revolutionary polymer wafer fabrication processes for Freescale s innovative Redistributed Chip Package (RCP).

• Designed and built unique tools for the manual fabrication of polymer wafers (panels) during the development of a new packaging process. The tool designs were later implemented into automated robotic tooling. There are three patents pending.

• Created non-degrading carrier attach and release process to temporarily allow panels to be held rigid during high-temperature front side circuit and dielectric build-up processes. Worked with the tool and chemical manufacturers to fully automate process step. Patent pending.

• Determined material sources and managed initial materials list for RCP processing. This list was used to create a bill of materials (BOM), materials inventory planning, and just-in-time delivery. Directed facility planners and contractors in design and layout of chemical storage and waste treatment facilities for the RCP manufacturing line.

Education

Master of Science, Chemistry Arizona State University, Tempe, Arizona

Bachelor of Science, Chemistry University of Cincinnati, Cincinnati, Ohio

Professional Experience

Faraday Solutions LLC, Chandler, AZ March 2009 - Present

Founder, Materials and Plating Specialist. Created consulting business to assist companies in

determining materials sets and processes for development of solar, medical and semiconductor products.

•Currently developing process and material sets for potential medical device application.

Quest Product Development Corp., Denver, CO.

Freescale Semiconductor Inc., Tempe, AZ 2004 - 2009

Distinguished Member of the Technical Staff. Initiated development of revolutionary polymer wafer fabrication processes for Freescale s innovative Redistributed Chip Package (RCP). Freescale additionally intends to

license RCP to subcontractors.

• Designed and built unique tools for manual fabrication of polymer wafers (panels) during development of new packaging process. Concepts and ideas were implemented into

automated robotic tooling. Three patents pending.

• Created non-degrading carrier attach and release process to temporarily allow panels to be held rigid during high-temperature front side circuit and dielectric build-up

processes. Worked with the tool and chemical manufacturers to fully automate process step. Patent pending.

• Developed process to prevent epoxy resin from bleeding onto semiconductor die bond pads during cure. This process was crucial to improving yield of RCP packages. Patent pending.

• Determined source and managed initial materials list for RCP processing. This list was used to create a bill of materials (BOM), materials inventory planning, and just-in-time delivery. Determined chemical usage rates and wastewater treatment plans based on the material data in this list.

• Directed facility planners and contractors in design and layout of chemical storage and waste Treatment facilities for the RCP manufacturing line.

Motorola Inc. Semiconductor Products Sector (SPS), Tempe, AZ & Austin, TX 1982 - 2004

Senior Member of the Technical Staff 2002 - 2004

• Managed implementation of lead-free plating process into Flip-Chip manufacturing operations for Motorola Semiconductor Products and managed the project for the initial development

of RCP.

• Directed research and development of polymer encapsulation, sputtered metal deposition, copper plating processes and selection of dielectric for demonstration of the feasibility

of the RCP process.

• Lead development and implementation of tin-silver and tin-copper plating baths and compatible bus (seed) metal etchants for manufacture of lead-free semiconductor devices for

Flip-Chip assembly. Freescale continues to use the lead-free plating process on all of its Flip-Chip devices.

Principal Staff Scientist, Tempe, AZ 1997 - 2002

• Provided failure analysis support for semiconductor package development team.

•Developed extremely low temperature grinding and polishing methods to allow cross-sectioning of the interfaces between hard and soft materials such as indium solder or polymeric

layers in contact with silicon. Patented.

• Performed SEM/EDX characterization on brittle solder joints and determined the cause to be chemical attack and depletion of elemental nickel. Proposed successful solutions to

improve joint reliability and saved Motorola over $5M from loss of business due to product returns.

• Solved GaAs through-via clearing and shorting issue by recognizing an interaction between gold and resist during plasma strip. Implemented the use of a gold before plasma

eliminating the issue and saving Motorola loss of a $10M customer.

Senior Staff Scientist,Tempe, AZ/Austin, TX 1995 - 1997

• Created and transferred Low-Cost Bump process to Motorola s manufacturing facility in Austin, Texas.

• Developed electroless nickel bath inhibitor to control a poorly understood phenomenon in electroless metal deposition processes. Without this inhibitor electroless nickel plating on wafers would not have been manufacturable.

Engineer/ Sr. Scientist, Phoenix, AZ 1982 - 1995

• Assumed different engineering roles in semiconductor product development eventually focusing on Flip-Chip package development.

Co-invented solder bumping process for Flip-Chip attach of a GaAs optical display for use in the worlds first sub-miniature monochromatic digital display. Patented.

• Developed two etchant formulations and processes to allow manufacture of plated inductors on silicon. Etchants and processes are also used in the fabrication on-wafer chip-array burn-in circuitry. Patented.

• Developed a fountain wafer plating cell to control flow and current effects during electrolytic deposition of soft metals such as indium tin and lead. Patented.

Patents

• 2010/0081234

• 2008/0182363 Method for forming a microelectronic assembly including encapsulating a die using a sacrificial layer

• 2007/0210427

• 2010/0078808 Packaging having two devices and method of forming thereof

• 2009/0061564 Method of packaging an integrated circuit device

• 2009/0057849 Interconnect in a multi-element package

• 7802359 Electronic assembly manufacturing method

• 7741151

• 7595226

• 7442581 Flexible carrier and release method for high volume electronic package

• 7078796

• 6974776

• 6953985

• 6949398

• 6302775

• 5912510

• 5674780 Method of forming an electrically conductive polymer bump over an aluminum

• 5593903

• 5587342

• 5411400

• 5409567

• 5391285

• 5072873

• 5028454

• 4946376

• 4787958 Method of chemically etching TiW and/or TiWN

PublicationsAdvanced Packaging: The Redistributed Chip Package, Keser, B. Amrine, C. Trung Duong Hayes, S. Leal, G. Lytle, W. Mitchell, D. Wenzel, R. Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM '07. IEEE, Sept. 30 2007-Oct. 2 2007

The Redistributed Chip Package: A Breakthrough for Advanced Packaging, B. Keser, C. Amrine, Trung Duong, O. Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, R. WenzelElectronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th., May 29 2007-June 1 2007 Page(s):286 291

Applying a Methodology for Microtensile Analysis of Thin Films, B. Yeung, W.Lytle, V. Sarihan, D.T. Read, Y. Guo, Solid State Technology, (2002) 125-129

Electroless Nickel and Void-Free Solder Printing: A Low Cost Bumping Approach, W.H.Lytle, T. Fang, InterPACK 01, 7/2001

Microtensile Methodology for Mechanical Characterization of Thin Films, B. Yeung, W.Lytle, V. Sarihan, D.T. Read, Y. Guo, 2001 ASME International mechanical Engineering Congress, 11/11/2001

Ethlylene Glycol Ether Free Solder Solder Paste Development, T. Fang, L. Li, W.H.Lytle Journal of Electronic Materials,v30, 8 2001

Physical design and assembly process development of a multichip package containing a light emitting diode (LED) array die, R. Bonda, Treliant Fang, K. Kaskoun, W.H. Lytle, B. Marlin, G. Swan, J.W. Stafford, G. Tam, Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on. 12/1997; 20(4):389-395.

Conductive polymer bump interconnects, Jong-Kai Lin; Drye, J.; Lytle, W.; Scharr, T.; Subrahmanyan, R.; Sharma, R.;Electronic Components and Technology Conference, 1996. Proceedings., 46th, 28-31 May 1996 Page(s):1059 1068

Application of a CFD tool in designing a fountain plating cell for uniform bump plating of semiconductor wafers, Tien-Yu Tom Lee, W.H. Lytle, B. Hileman

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on. 03/1996; 19(1):131-137.

Book Chapter: Microelectronic Packaging, New Trends in Electrochemical Technology, M.Datta, T. Osaka, J.W. Schultze, (eds.), Chapter 8, Pb -free flip-chip technologies, Darrel R. Frear, William H. Lytle, CRC Press (2005), 225-252

Professional Societies

IEEE-CPMT, MEPTEC, IMAPS, American Chemical Society, ChemPharma

Training

Six Sigma Methodology, Green Belt in Statistics, Chemical Waste Handling

Copyright 2009-2010 Faraday Solutions, LLC.

Web Design by Erin Lanus.

Copyright 2009-2010 Faraday Solutions, LLC.

Web Design by Erin Lanus.

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