Engineering Engineer

***.***@*****.***

OBJECTIVE

I want to work with smart people on a great team making awesome *ware

EXPERIENCE

Member of Te nical Sta, Centaur Te nology (acquired by VIA); Au in TX Present

I o en work on new and experimental proje s, which means that I ve been exposed to everything under the sun, but I

can t talk about what I ve done lately.

Right now, I m working on processor and chipset security, but I can t say much more than that.

A few proje s ago, we were experimenting with adding a front-end for another in ru ion set to our processor. Over the

course of six months, I helped reverse engineer the ISA, created the archite ural simulator, picked apart Linux (Android)

to make it work in the simulator, wrote RTL for about half of the translator, along with microcode for the microcoded

in ru ions, and created the te generator that found the r bugs on the proje .

I ve been here for seven years, so there s no way to succin ly describe my responsibilities. I ve done everything from

automated theorem proving for formal veri cation to adding fault tolerance to a di ributed sy em to po -silicon lab

debug. In short, I nd hard problems and solve them.

Resear Assi ant, Ultrafa Optics and Fiber Communications Lab; Lafayette, IN

Sped up parallel ( wavelength) polarimeter by x, from Hz to kHz MATLAB and C++

Designed and built Fourier transform spe roscopy interferometer MATLAB and C++

Tea ing Assi ant, Purdue University; We Lafayette, IN

TA for two se ions of Linear Circuit Analysis II and two se ions of Ele romagnetic Fields

Volunteer, Red Cross; We Lafayette, IN

Intern, IBM; Au in, TX Summer

Semi-formal / con rained random POWER completion unit fun ional veri cation VHDL

Wrote te benches that created reasonable in ru ion retirement pa erns VHDL

Resear Assi ant, VLSI Design and Design Automation Laboratory; Madison, WI

Studied high level RLC interconne modeling and optimization

Studied e e of power gating and clock gating on microprocessor power consumption SimpleScalar (C++)

Intern, Micron Te nology; Boise, ID Summer

Backend te, chara erization, and design veri cation for low power NOR ash Perl

Resear Assi ant, Spatial Sy ems Resear Laboratory; Madison, WI

Studied tilings and related combinatorial models, e.g., alternating sign matricies, square ice

EDUCATION

Sele ed Graduate Courses: Computer Archite ure, Interconne Modeling and Optimization, VLSI Design, Digital Logic

Synthesis Algorithms, Computational and Stati ical Learning eory, Empirical Methods in Engineering, Matrix eory,

Error-Corre ing Codes, Adv. Math for Engineers, eory of Di erential Equations, Algorithms

Sele ed Upper Division Undergraduate Courses: CMOS VLSI Design, Te ing and Design for Te ability, Digital Sy ems

Design and Synthesis, Databases, Combinatorics

Ele rical and Computer Engineering - Present

University of Texas, Au in, TX

I m enrolled mo ly so that I can learn new things, ju for a change of pace. I take the occasional course (Computational

Learning eory, Empirical So ware Engineering, and Algorithms), and do a bit of research on the side (Algorithmic

Game eory, Empirical Studies in So ware Engineering

h p://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=, Evaluation & Assessment in So ware Engineering (EASE ),

h ps://sites.google.com/site/deangeli ech/publications/towards-evaluating-human-in ru able-so ware-agents, International Conference on

Interfaces and Human Computer Intera ion (ICIHCI )

GPA: .

GRE: . / / (analytical/math/verbal)

M.S.E. Ele rical and Computer Engineering

Purdue University, We Lafayette, IN

GPA: . ( . in MS courses)

GRE: / / (analytical/math/verbal)

B.S. Math and B.S. Computer Engineering, with di in ion

University of Wisconsin, Madison, WI

GPA: . ( . in upper-division and graduate level ECE courses)

NON WORK PROJECTS

Sega sy em on Xilinx Vertex FPGA; translated Z in ru ions into RISC ops Verilog and VHDL

S- : Ninety-Nine Scala Problems Scala with JUnit

Formal veri cation of a secure hypervisor ACL

Proje Euler F# and bluespec

HONORS AND AWARDS

MCD Fellowship -

Burton D. Morgan Entrepreneurship Competition Semi-Finali

David Ross Fellowship ( ve years of guaranteed funding) -

SRC undergraduate research grant -

Dean s Li -

VIGRE undergraduate research funding

AP Scholar with di in ion

MISCELLANEOUS

Languages: English mother tongue. Once- uent Vietnamese. Once-fun ional (now moribund) Japanese and French. Will-

ing (and eager) to learn any language

A ivities: O cer and organizer for Students in So ware Engineering; member of ARG climbing team, UT climbing team,

and occasional antendee of UT sciences Toa ma ers club

Work Authorization: U.S. Citizen

h ps://github.com/danluu/sega-sy em-for-fpga

h ps://github.com/danluu/ninety-nine-scala-problems

h ps://github.com/danluu/secvisor-formal-veri cation

h ps://github.com/danluu/Proje -Euler

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