Engineer Design

William Dittenhofer

Email: abqc73@r.postjobfree.com

Address: **** ****** **

City: Loveland

State: CO

Zip: 80538

Country: USA

Phone: 719-***-****

Skill Level: Experienced

Salary Range: $120,000

Primary Skills/Experience:

See Resume

Educational Background:

See Resume

Job History / Details:

FPGA Development Engineer

ASIC, FPGA Design and Verification of Custom Embedded Processors, DSP, Memory Controllers,

Hi Speed Serial Interfaces, Storage, Inter Connect Fabric, Power Control, Caches, Video, Graphics,

Sonar, SatCom and Software Defined Radio (SDR). Multi Language fluency with SystemVerilog,

Verilog, VHDL, SystemC, SVA. Experience with Synthesis (SYNOPSYS, SYNPLICITY, Xilinx and

Altera, System Generator). Clock Domain Analysis (0in CDC), OVM, SVA, Java

Top Secret Clearance.

SPECIALTIES

* Digital Hardware Design (ASIC/FPGA, DSP, Custom Embedded Processor, SOC)

* DSP Implementation (CATAPULT, MATLAB, DSP Builder, System Generator )

* Digital Hardware Verification (AVM,OVM, SystemC, SystemVerilog, SVA)

* Custom design for ICE PIC6, Spectrum FGPA based SDR platforms.

* System Modeling (SystemC, C++, Java)

EDUCATION

* MSEE, University of Virginia, 1993

EXPERIENCE

2012 to Present TASC Technical Services

FPGA Designer Image Processing

Designed RTL (under contract) for IR sensor Image Processing algorithms targeting Altera Stratix IV. My role consisted of converting C++ model to fixed point RTL, verifying RTL with C++ model using a hybrid test bench of VHDL, SystemVerilog and SystemC. I am assisting software with lab validation.

2010- 2012 Modern Technology Solutions, Inc., Colorado Springs, CO

Principal HW Design Engineer

Delivered Software Defined Radio (SDR) FPGA design (under contract) to USAF Rapid Reaction Branch in 4.5 months as sole contributor. Project required a proprietary custom embedded processor, complex algorithms, DSP, multiple clock domains, Hyper Transport, PCIE, custom and commercial IP. Utilized ICE V6M (Virtex 6) SDR platform, SystemVerilog, VHDL, Matlab, Linux, Perl, C++. Due to lack of qualified personnel, I assumed roles of Design Verification and System Integration, System Test. I implemented a large test bench and test suite utilizing SystemVerilog, and because of this was able to finish hardware debug in two months. I completed integration of this project by producing 80% of the Java code, learning JAVA (required) on the fly.

Implemented and used Linux based design and verification system encompassing design rules, HDL tools, simulators, revision control (subversion) and documentation. Installed and managed this system on a network based server.

2007-2010 Hewlett-Packard, Fort Collins, CO

FPGA Design Engineer, ASIC Verification Engineer

Designed FPGA based IP using SystemVerilog, Synplicity for high availability HP servers. This included fabric and high speed serial interfaces, power sequencing, motor control, noise cancellation, embedded processor support, etc. Assisting conversion of Altera based designs to ASIC for cost reduction.

Modeled and verified a high performance Fabric Chip Set for high end HP servers using SystemC and C++. Specific duties were for PCIE Root Complex section.

Under contract to USAF Rome Development Lab, implemented FPGA based DSP RTL including filters, FFT and Digital Wave Filters. I was tasked with the modeling a high performance multiple MAC DSP processor with custom instruction set using SystemC / C++. Model will be used for architecture and performance analysis. I was the designated lead for RTL design team, which used SystemVerilog, OVM and the SystemC based model for verification.

I was a Co-Author of DVCON paper "SystemC vs. SystemVerilog" and panelist for SystemC/C++ synthesis at NASCUG. Also a Member of HP Corporate EDA and Methodology team, OVM Industry Advisory Board.

2002-2007 AMI Semiconductor Colorado Springs, CO

Senior Staff Digital Designer, Team Lead

Lead Engineer for a DSP embedded processor. This design was a pipelined, low power, 20 bit fixed point Dual Harvard embedded processor. The design was implemented in both an ASIC and an FPGA based emulation platform. Responsible for RTL implementation from architectural and conceptual drawings, architect of the processor specific SystemC/C++ based test bench. My direct contribution was the program control, pipeline, instruction decode, arithmetic unit, data path, logical unit, Verilog / SystemC co simulation. The product can be seen as http://www.sounddesigntechnologies.com/products_Wolverine.php

Verification lead for a complex 1.4 million gate multi-processor SOC and mixed signal CODEC. The SOC consisted of mixed signal and DSP units, proprietary wireless interface, our own embedded micro controller (see above), and wave digital filters. Our team developed DV procedures, coding standards, modeling and verification methods based on SystemC. This resulted in the sites first single pass ASIC tape out.

Assisted remote team with mixed signal ASIC that analyzes blood chemistry. Duties included algorithm modeling, RTL coding, verification. Continued support for this project modeling a PID mixed signal control loop using C++/ SystemC, and tied this into the RTL verification process.

Author of 4 SystemC based conference papers, including "Modeling Techniques with SystemC", "Design and Verification of a Processor using SystemC, VHDL and Verilog" which was voted best design paper at DVCON 20004.

1999 - 2002 PalmChip Corporation, Loveland CO

Staff HW Engineer, Architect

Designed highly configurable Ethernet, PCI block, DMA Interface, Memory Controllers (SDR and DDR SDRAM, FLASH) cores. Integrated these into ARM7, ARM9 based SOC platforms for custom applications. These applications included Telecom, RAID, Disk Drive Controllers, Printers, and Medical Products.

As working manager of IP development group, Responsibilities include architecture, design, and verification of new IP, maintenance of legacy products. The group became a profit center with sales to external customers (Intel, TI, and LSI Logic). My key contribution was implementing DV standards and practices.

As Staff Architect, duties include determining the next generation of PalmChip's platform based Multi-Processor SOC architectures for Telecom (OC-48, 192), 3G wireless platforms. Work with established customers to improve performance of Palmchip first generation platforms. Also specify improvements, upgrades to legacy IP, as well as assist less experienced engineers with new designs. Act as a technical closer for sales. Presented paper titled "Configurable DMA Controller for an SOC" at DesignCon2000.

SPECIALIZED TRAINING

* System Generator, DSP Builder, Catapult

* Xilinx Training (Embedded Processors, DSP implementation, SystemVerilog)

* Altera Training (Embedded Processors, DSP Design, FPGA to ASIC conversion)

* Modeling, System Verilog Design and Verification, OVM Adopter

* SystemC /C++ for System Modeling

* PCIE System Architecture

RECOGNITION

* Best Paper at DVCON 2004

* Panelist for NASCUG Abstract Synthesis (C++, SystemC to RTL synthesis)

PROFESSIONAL MEMBERSHIPS

* NASCUG (N. American SystemC Users Group)

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