Control Assistant

Phone: 603-***-****

Email: *******.**@***.***

Qiaoyan Yu Kingsbury Hall W215

University of New Hampshire, NH 03824

Homepage: http://www.ece.unh.edu/qiaoyan

EDUCATION

Ph.D. Electrical and Computer Engineering (May 2011)

UNIVERSITY OF ROCHESTER, ROCHESTER, NY 14627

Dissertation: Transient and Permanent Error Management for Networks-on-Chip

M.S. Electrical and Computer Engineering (May 2007)

UNIVERSITY OF ROCHESTER, ROCHESTER, NY 14627

M.S. Information Science & Electronic Engineering (March 2005)

ZHEJIANG UNIVERSITY, HANGZHOU, CHINA

B.S. Telecommunications Engineering (July 2002)

XIDIAN UNIVERSITY, XI AN, CHINA

EMPLOYMENT HISTORY

Assistant Professor (Aug. 2011-Present)

DEPT. OF ELECTRICAL AND COMPUTER ENGINEERING, UNIVERSITY OF NEW HAMPSHIRE

Research interests: error control for networks-on-chip, fault-tolerance for many-core systems, and emerging

nanoelectronics.

Instructors for courses: Computer Organization, Digital Systems, Electronic Design II

Postdoctoral Scholar (May 2011-Jul. 2011)

EDISON RESEARCH GROUP, ECE DEPARTMENT, UNIVERSITY OF ROCHESTER

Error control for networks-on-chip

Research Assistant (Aug. 2006-Apr. 2011)

EDISON RESEARCH GROUP, ECE DEPARTMENT, UNIVERSITY OF ROCHESTER

Reliable backend integrated hybrid photonic-electronic networks-on-chip

Dual-layer cooperative error control for nanoscale networks-on-chip

Ballistic deflection transistor, simulation, device and circuit designs

Leakage management techniques for nanoscale CMOS memories

Internship (Jun. 2008-Aug. 2008)

SUPERCOMPUTER CENTER, UNIVERSITY OF CALIFORNIA, SAN DIEGO

Developed a flexible and parallel simulator for networks-on-chip with error control mechanisms (Sponsored by

NSF Cyber-Infrastructure Experience for Graduate Students CIEG)

Teaching Assistant (Aug. 2005-Jul. 2006)

ECE DEPARTMENT, UNIVERSITY OF ROCHESTER

Courses: Electromagnetic Waves; Computer Organization

Research Assistant (Sept. 2002-Mar. 2005)

ZHEJIANG PROVINCE HIGH TECHNIQUE PROJECT, ZHEJIANG UNIVERSITY, CHINA

Developed 16-bit fixed-point digital signal processor (DSP)

PROFESSIONAL DISTINCTIONS

Final list of the Best Paper, 5th ACM/IEEE Intl. Symp. on Networks-on-Chip, 2011

Nominated for an Outstanding Dissertation Award in engineering and applied sciences, University of

Rochester, 2011

Best Ph.D. Dissertation Award in the ECE Department, University of Rochester, 2011

Rochester Scholars Pre-College Programs Sponsored by University of Rochester, 2010

Qiaoyan Yu Curriculum Vitae 2/3

NSF Cyber-Infrastructure Experiences for Graduate Students (CIEG), 2008

Honor Graduate of Zhejiang Province in P.R. China, 2005

Best Student Paper, 7th Intl. Conf. on Solid-State and Integrated-Circuit Technology, 2004

First Prize Scholarship for top 5 Graduate of Zhejiang University, 2002-2005

Honor Undergraduate of Shaanxi Province in P.R. China, 2002

First Prize Scholarship for top 5 Undergraduate of Xidian University, 2000-2002

Outstanding Undergraduate Scholarship of Xidian University, 1999

PROFESSIONAL SERVICES

Associate Editor for Journals:

J. Circuits, Systems, and Computers (JCSC)

Reviewer for Journals:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

IEEE Transactions on Circuits and Systems Part II: Express Briefs (TCAS-II)

IEEE Transactions on Reliability

IET Computers & Digital Techniques

Journal of Electronics & Information Technology

Chinese Journal of Electronics

Program Committee for Conference:

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

IEEE International Symposium on Embedded Multicore System-on-Chip

PROFESSIONAL MEMBERSHIP

IEEE

IEEE Circuits and Systems Society

ACM

PUBLICATIONS

Book

1. Q. Yu and P. Ampadu, Transient and permanent error control for networks-on-chip, ISBN 978-1-4614-

0961-8, Springer Press, New York, 2011.

Book Chapter

2. P. Ampadu, B. Fu, D. Wolpert and Q. Yu, Adaptive voltage control for energy-efficient NoC links, in

Low-Power Networks on Chip, C. Silvano, M. Lajolo, G. Palermo, Ed. Milan: Springer Press, 2011, pp. 45-69.

Refereed Papers in Journals

3. Q. Yu, M. Zhang and P. Ampadu, Addressing network-on-chip router errors with inherent information

redundancy, ACM Trans. on Embedded Computing Syst.-Special Issue on On-Chip and Off-Chip Network Archit.

(in press).

4. Q. Yu and P. Ampadu, Dual-layer adaptive error control for network-on-chip links, IEEE Trans. on Very

Large Scale Integr. (VLSI) Syst., vol. 20, no.7, pp.1304-1317, July 2012.

5. Q. Yu and P. Ampadu, A dual-Layer method for transient and permanent error co-management in NoC

links, IEEE Trans. on Circuit and Systems II-Express Briefs, vol. 58, no. 1, pp. 36-40, Jan. 2011.

6. Q. Yu and P. Ampadu, A flexible parallel simulator for networks-on-chip with error control, IEEE Trans.

on Computer-Aided Design of Integr. Circuits and Syst. (TCAD), vol. 29, no. 1, pp.103-116, Jan. 2010.

Qiaoyan Yu Curriculum Vitae 3/3

7. Q. Yu and P. Ampadu, Adaptive error control for nanometer scale NoC links, IET Computers & Digital

Techniques-Special Issue on Advances in Nanoelectronics Circuits and Syst., vol. 3, no. 6, pp. 643-659, Nov. 2009.

8. D. Huo, Q. Yu, D. Wolpert and P. Ampadu, A simulator for ballistic nanostructures in a 2-D electron

gas, ACM J. on Emerging Technologies in Computing Syst. (JETC), vol. 5, no. 1, Article 5, Jan. 2009.

9. J. Chen. P. Liu, Q. Yao, C. Shi, D. Zheng, Q. Yu and L. Lai, MD16: 16-bit DSP processor with special

RISC philosophy, J. Circuits and Systems, vol. 12, no. 5, pp. 65-71,145, Oct. 2007.

10. Q. Yu, P. Liu and Q. Yao, Data hazard detection method for DSP with heavily compressed instruction

set, J. Zhejiang University(Engineering Science), vol. 39, no. 10, pp.1501-1506, Oct. 2005.

Refereed Papers in Proceedings

11. Q. Yu and P. Ampadu, Transient error management for partially adaptive router in network-on-chip

(NoC), in Proc. Intl. Symp. on Circuits and Syst. (ISCAS 12), pp. 1672-1675, May 2012.

12. M. Zhang, Q. Yu and P. Ampadu, Fine-grained splitting methods to address permanent errors in

network-on-chip links, in Proc. Intl. Symp. on Circuits and Syst. (ISCAS 12), pp. 2717-2720, May 2012.

13. Q. Yu, J. Cano, J. Flich and P. Ampadu, Transient and permanent error control for high-end

multiprocessor systems-on-chip, in Proc. 6th ACM/IEEE International Symposium on Networks-on-Chip

(NoCS 12), pp. 169-176, May 2012.

14. Q. Yu, M. Zhang and P. Ampadu, Exploiting inherent information redundancy to manage transient

errors in NoC routing arbitration, in Proc. 5th ACM/IEEE International Symposium on Networks-on-Chip

(NoCS 11), pp. 105-112, May 2011.

15. Q. Yu, M. Zhang and P. Ampadu, A comprehensive networks-on-chip simulator for error control

explorations, in Proc. 5th ACM/IEEE Intl. Symp. on Networks-on-Chip (NoCS 11), pp. 263-264, May 2011.

16. Q. Yu and P. Ampadu, Transient and permanent error co-management method for reliable networks-on-

chip, in Proc. 4th ACM/IEEE Intl. Symp. on Networks-on-Chip (NoCS 10), pp. 145-154, May 2010.

17. Q. Yu, B. Zhang, Y. Li and P. Ampadu, Error control integration scheme for reliable NoC, in Proc. 2010

IEEE Intl. Symp. on Circuit and Syst. (ISCAS 10), pp. 3893-3896, May 2010.

18. Q. Yu and P. Ampadu, Dual-layer cooperative error control for a reliable nanoscale NoC, in Proc. 24th

IEEE Intl. Symp. on Defect and Fault Tolerance in VLSI Sys. (DFT 09), pp. 431-439, Oct. 2009.

19. V. Kaushal, M. Margala, G. Guarino, Q. Yu, W. Donaldson, R. Sobolewski, P. Ampadu, A study of

effects of deflector position variation on leakage currents in ballistic deflection transistors, in Proc. 2009

IEEE Nanotechnology Materials and Devices Conf., Traverse City, MI, June 2-5 2009.

20. Q. Yu and P. Ampadu, Adaptive error control for NoC switch-to-switch links in a variable noise

environment, in Proc. 23rd IEEE Intl. Symp. on Defect and Fault Tolerance in VLSI Sys. (DFT 08), pp. 352-360,

Oct. 2008.

21. Q. Yu and P. Ampadu, Configurable error correction for multi-wire errors in switch-to-switch SoC links,

in Proc. 21st Annual IEEE Intl. SoC Conf. (SoCC 08), pp. 71-74, Sept. 2008.

22. Q. Yu and P. Ampadu, Adaptive error control for reliable systems-on-chip, in Proc. Intl. Symp. on Circuits

and Syst. (ISCAS 08), pp. 832-835, May 2008.

23. D. Huo, Q. Yu and P. Ampadu, A ballistic nanoelectronic device simulator, in Proc. Intl. Symp. on

Nanoscale Architectures (NanoArch 07), pp. 38-45, Oct. 2007.

24. Q. Yu and P. Ampadu, Cell ratio bounds for reliable SRAM operation, in Proc. 12th IEEE Intl. Conf. on

Electronics, Circuits and Syst. (ICECS 06), pp. 1192-1195, Dec. 2006.

25. B. Fu, Q. Yu, and P. Ampadu, Energy-delay minimization in nanoscale domino logic, in Proc. 16th Great

Lakes Symp. on VLSI (GLSVLSI 06), pp. 316-319, Apr. 2006.

26. Q. Yu, P. Liu, Q. Yao and K. Chen, A functional verification method for pipelined DSP, in Proc. 7th

IEEE Intl. Conf. on Solid-State and Integrated-Circuit Technology, vol. 3, pp. 2055-2058, Oct. 2004.

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