Dr. Masud H. Chowdhury

Associate Professor, Department of Computer Science and Electrical Engineering, University of Missouri Kansas City

Address: Room No. 570-E RHFH, 5110 Rockhill Road, Kansas City, MO 64110-2499

Email: abqbzb@r.postjobfree.com, abqbzb@r.postjobfree.com

Education Doctor of Philosophy in Computer Engineering (2004)

Northwestern University, Evanston, Illinois 60208, USA

Bachelor of Science in Electrical and Electronic Engineering (1998)

Bangladesh University of Engineering and Technology, Dhaka 1000, Bangladesh

Research 1. High performance issues of VLSI Circuits

a. System-on-a-Chip (SOC) and Multi-Core Design Issues

Interests

b. Subthreshold Design for Ultra Low Power Applications

c. Technology Scaling and Future Technology (RF Interconnect) for Integrated Circuits

d. Leakage Reduction and Power Gating Interconnect

e. Noise, Timing and Power Issues of Integrated Circuits

2. Optically Reconfigurable VLSI Circuits

3. Cross-Disciplinary Issues in Power Electronics and VLSI Design

a. On-chip Voltage Regulation

4. Cross-Disciplinary Issues in Nanoelectronics and Green Energy Technology

a. Carbon Nanotube (CNT) and Graphene based Nanoelectronic Circuits and Devices.

b. CNT-based Solar Cell Design

Work 1. Associate Professor (Current), Computer Science and Electrical Engineering, University of

Missouri Kansas City (UMKC)

Experiences

2. Assistant Professor, Electrical and Computer Engineering, University of Illinois at Chicago

3. IBM Summer Internship, IBM Austin Research Lab, Austin, Texas, USA

4. Graduate Research Assistant, Northwestern University, Evanston, IL 60208, USA

5. Teaching Associate, Northwestern University, Evanston, IL 60208, USA

6. Lecturer, Department of Computer and Communication Engineering, IIUC, Bangladesh

Awards & 1. Senior Member, Institute of Electrical and Electronic Engineers (IEEE)

2. College of Engineering Teaching Award 2009, University of Illinois at Chicago, IL 60607, USA

Honors

Best Paper Award, IEEE 10th WMSCI 2006, Orlando, Florida, USA

3.

4. Best Poster Award, ECE EXPO Day 2003, Northwestern University

Best Paper Award, IEEE 5th WMSCI 2001, Orlando, Florida, USA

5.

6. Merit Scholarship, Secondary & Higher Secondary Education Board, Bangladesh, 1990-1991,

7. Technical Scholarship, Bangladesh University of Engineering and Technology, 1994-1998

8. Best Student of the School, Saint Placid s High School, Chittagong, Bangladesh, 1989

9. Best Student of the Class, Saint Placid s High School, Chittagong, Bangladesh, 1989

10. Government Junior High School Merit Scholarship, Bangladesh Education Ministry, 1987

Professional and Synergistic Activities

Chair-Elect (May 2012)

IEEE VLSI Systems and Applications (VSA) Technical Committee

Associate Editor (2009-Current):

Journal of Circuit, Systems and Signal Processing (CSSP), Springer Publication

Symposium Chair:

Computer Design & VLSI Symposium (CSIE 2009), March 31 - April 2, 2009, Anaheim, CA, USA

Conference Track Chair:

1. VLSI Systems, Architectures and Applications, ISCAS 2013, May 19-23, 2013, Beijing, China

2. Digital Circuit, 22nd International Conf. on Microelectronics, Dec. 19-22, 2010, Cairo, Egypt

3. Digital Design and Memories, 10th IEEE International NEWCAS Conference, June 17-20, Montreal, Canada

Special Session Organizer:

1. Sub-Threshold Design for Ultra Low Power and Ultra-Dynamic Voltage Scaling, IEEE ISCAS 2009

2. Cross Disciplinary Research in Signal and Image Processing, and VLSI Circuit Issues, IEEE ISIC 2009

3. Modeling of Carbon Nanotubes (CNT), and Application of CNT in Solar Cell Design, IEEE ISIC 2009

Program Committee Member:

1. IEEE Circuits and System Society (CAS) VSA Track TPC (2005-2012)

2. IEEE Great Lake Symposium on VLSI (GLSVLSI)

3. World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI)

4. IEEE International Conference on Circuits and Systems for Communications (ICCSC)

5. International Conference on Microelectronics (ICM)

6. IEEE NEWCAS Conference

7. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

Conference Session Chair:

Chaired Over Twenty Five (25) Sessions in Various IEEE and ACM Conferences

NSF Panel Review:

1. MNS 508 Panel Meeting for May 28-29, 2008

2. OISE Proposal Review (NSF 11-508), April, 2011

3. OISE Proposal Review (NSF 11-508), September, 2011

Journal and Conference Review:

Served as the Reviewer for 15 different Journals and Transactions

Served as the Reviewer for 7 different IEEE and ACM Conferences

Invited Talks and Seminars:

1. Design and Research Projects for Undergraduate Students, April 2011, Northern Illinois University (NIU)

2. History of Electronics, ECE Open House for High School Students and Parents, October 2007, UIC

3. Computer Engineering Education and Career Prospects, ECE Open House, March 2007, UIC

4. Remarkable Journey of Integrated Circuit (IC) Technology, ECE Open House, March 2006, UIC

5. "Effects and Analysis of Electrostatic and Electromagnetic Coupling in Deep Sub-Micron VLSI Circuits", ECE

Distinguished Speaker Seminar Series, September 2004, Illinois Institute of Technology (IIT), Chicago, Illinois

6. Issues of System-On-a-Chip (SOC) design, September 2002, IIUC, Chittagong, Bangladesh

7. "High Performance Issues in Deep Submicron VLSI Circuits ", March 2005, IIUC, Bangladesh

Student Advising Records:

Current Students at UMKC: 3 PhD and 2 MS (Thesis) Students.

PhD Students Supervised a UIC: 3 (Currently employed by Intel, Synopsys and Qualcomm).

MS Thesis Students Supervised at UIC: 5 (Currently employed by Apple, Intel, and Micron)

MS non-Thesis Students Supervised at UIC: 15

Undergraduate Research and Project Students Supervised at UIC: 20

Current Grants and Pending Proposals

Active Grants:

1. Title: Carbon Nanotube based Solution for the next Generation Logic Circuits

Agency: Air Force Office of Scientific Research (AFOSR)

Type of Funding: SBIR Phase-I (a Collaborative Effort between Small Business and University)

Collaborators: Digital Optics Technologies (DOT) INC. and University of Illinois at Chicago (UIC)

Budget Allocated: $150K

Duration: 12 Months, December 2011 - November 2012

Dr. Chowdhury s Role: UIC PI and Overall Project Coordinator

2. Title: Next Generation Nanoelectronic Circuit Elements using Graphene Nanoribbon Carbon

Agency: Air Force Office of Scientific Research (AFOSR)

Type of Funding: SBIR Phase-II

Collaborators: Digital Optics Technologies (DOT) Inc., UMKC, Northwestern University and Michigan

Molecular Institute (MMI)

Requested Budget: $750K

Duration: 2 Years, January 2013 December 2014

Dr. Chowdhury s Role: UMKC PI and Overall Project Coordinator

Pending Proposals:

3. Title: Ultrafast Automatic Target Recognition System using a Hybrid Holography-VLSI Correlator Invariant

under Shift, Rotation and Scaling.

Agency: Air Force Office of Scientific Research (AFOSR)

Type of Proposal: Regular Proposal

Collaborative proposal including UMKC and Northwestern University

Requested Budget: $900K, (UMKC: $400K and Northwestern: $500K)

Duration: 5 years, January 2013 December 2017

Dr. Chowdhury s Role: UMKC PI

4. Title: Next Generation Biomimetic Synaptic Circuit - From Silicon to Graphene Nanotechnology

Agency: University of Missouri Research Board (UMRB)

Type of Proposal: Exploratory Grant Proposal

Requested Budget: $45K

Duration: 12 Months, January 2013 December 2013

Dr. Chowdhury s Role: PI

5. Title: Graphene Based Nanotechnology For Next Generation Solar Energy Solution

Agency: Department of Energy (DOE)

Type of Proposal: Early Career Research Program

Requested Budget: $780K

Duration: 5 years, July 2013 June 2018

Dr. Chowdhury s Role: PI

Patents and Publications

Patent Disclosures:

1. M. H. Chowdhury, C. S. Amin, and Y. I. Ismail, Realizable Reduction of RLC Circuits Using Node Elimination.

Patent pending with Semiconductor Research Corporation

2. M. H. Chowdhury and J. Gjanci, A Hybrid Voltage Regulation Scheme for Multicore System-on-Chip (SOC),

Provisional Patent Application Submitted by the UIC Office of Technology Transfer.

3. M. H. Chowdhury and J. Xu, Fast Waveform Estimation (FWE) for Timing Analysis, Provisional Patent

Application Submitted by the UIC Office of Technology Transfer.

Referred Journal Papers:

1. S. Subash, J. Kolar and M. H Chowdhury, A New Spatially Rearranged Bundle of Mixed Carbon Nanotubes as

VLSI Interconnection, Accepted in the IEEE Transaction on Nanotechnology (TNANO) (Paper ID # TNANO-

00322-201).

2. J. Gjanci and M. H Chowdhury, A Hybrid Scheme for On-Chip Voltage Regulation in System-On-A-Chip (SOC),

IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 11, Nov 2011, pages: 1949-1959

3. J. Xu and M. H. Chowdhury, Fast Waveform Estimation (FWE) for Timing Analysis, IEEE Transaction on VLSI

(TVLSI), May 2011, Volume 19, Issue 5, Pages: 846-856.

4. Roy, J. Xu and M. H. Chowdhury, Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled

RLC Interconnects for Different Switching Patterns, IEEE Transactions on VLSI, Feb 2010, Vol. 18(2), pp 338-342

5. M. H. Chowdhury and Y. I. Ismail, Realistic Scalability of Noise in Dynamic Circuits, IEEE Transaction on Very

Large Scale Integration (TVLSI), Volume 14, Issue 6, June 2006 Page(s): 637 - 641

6. C.S. Amin, M. H Chowdhury and Y.I. Ismail, Realizable reduction of interconnect circuits including self and

mutual inductances, IEEE Transactions on CAD (TCAD), Volume 24, Issue 2, Feb. 2005 Page(s): 271 277

7. M. H. Chowdhury, P. Khaled and J. Gjanci, An Innovative Power Gating Technique for Leakage and Ground

Bounce Control in System-on-a-Chip (SOC), Circuits, Systems & Signal Processing (CSSP), Springer, Feb 2011,

vol. 30, 89-105.

8. M. H. Chowdhury and Y. I. Ismail, "Behavior and Analysis of Deep Sub-micron Integrated Circuits Including Self

and Mutual Inductances, " Circuits, Systems & Signal Processing (CSSP), Springer, Feb 2008, vol.27, no.1, pp.23-34

9. M. Rahaman and M. H Chowdhury, Energy Efficiency of Error Control Coding in Intra-Chip RF/Wireless

Interconnect Systems, Microelectronics Journal, Elsevier, Volume 41, No 1, January 2010, Pages 33-40

10. J. Xu, V. Nigam, A. Roy, and M. H. Chowdhury, Compound Noise Separation in Digital Circuits Using Blind

Source Separation, Microelectronics Journal, Elsevier, Volume 39, Issue 8, August 2008, Pages 1083-1092

11. S. Subash and M. H Chowdhury, Mixed Carbon Nanotube Bundles for Interconnect Applications, International

Journal of Electronics, Taylor & Francis, Vol. 96, No. 6, June 2009, Pages: 657 671

12. J. Xu, A. Roy, and M. H. Chowdhury, Power Consumption and BER of Flip-flop Inserted Global Interconnect",

Journal of VLSI Design, Volume 2007, Article ID 42829, 8 Pages, 2007

Invited Journal Papers:

13. J. Xu, M. H. Chowdhury, Circuit Level Issues of Interconnect Pipelining in Nanoscale Integrated Circuits, Journal

of Micro and Nano Systems (MNS), Bentham Science Publishers Ltd, In Press

14. S. Krishnamoorthy and M. H. Chowdhury, Compact Thermal Network Model: Realization and Reduction, Journal

of Integrated Computer-Aided Engineering (ICAE), Vol. 16, Number 2, 2009, Page(s): 131-140

15. J Xu, A Roy, and M. H. Chowdhury, Noise separation in analog integrated circuits using independent component

analysis technique, Journal of Integrated Computer-Aided Engineering, Vol.15, Number 2, 2008. Page(s): 163-180

Journal Papers (In Submission):

16. A. Roy and M. H Chowdhury, Simple Analytical Models for Propagation Delay and Crosstalk in RC Interconnects

for any Switching Patterns, submitted to Journal of VLSI Design.

17. M. Rahaman, and M. H. Chowdhury, A Unified Coding Approach for Addressing Crosstalk Delay, Energy and

Reliability for RLC Interconnects, Submitted to Circuits, Systems & Signal Processing (CSSP), Springer

18. M. Rahaman, and M. H. Chowdhury, Impact of Negative Capacitance Field-Effect Transistor-Based Interconnect

Drivers for Sub-threshold Circuits, Submitted to IEEE Transaction on VLSI (TVLSI).

19. Lin, Hui; Rahaman, Md. S.; Chowdhury, M., Micro-Architecture Framework for Power-aware Instruction

Permutation, Submitted to IET Circuits, Devices & Systems

20. P. Vora, and M. H. Choudhary, A Circuit Implementation for Dynamic Thermal Management Techniques

submitted to Microelectronics Journal, Elsevier

21. A. Roy and M. H Chowdhury, Accurate Modeling of Interconnect Capacitance in Multilevel Interconnect

Structures, submitted to Microelectronics Journal, Elsevier

22. M. Hefeida and M. H. Chowdhury, Improved Model for Wire-Length Estimation in Stochastic Wiring

Distribution, submitted to International Journal of Electronics, Taylor & Francis

Article in International Newspaper:

23. Masud H Chowdhury, Green future for Bangladesh through solar power generation, Daily New Age, 10/22/2011,

http://newagebd.com/newspaper1/special/37769.html

Selected Conference Papers:

1. M. Rahaman and M. H. Chowdhury, Exploiting Negative Quantum Capacitance of Carbon Nanotube FETs for Low

Power Applications, IEEE International Symp. on Circuits and Systems (ISCAS 2012), Seoul, South Korea, 17-20 May

2012.

2. P. Vora and M. H Chowdhury, A Circuit Implementation for Dynamic Thermal Management Techniques, IEEE

International Symp. on Circuits and Systems (ISCAS 2011), 15-18 May 2011, Rio de Janeiro, Brazil, pp 1668-1671.

3. M. Rahaman, Q. Duan and M. H Chowdhury, Spatial- and Temporal-Reliability Aware Design for Nano-Scale

VLSI Circuits, ISCAS 2011, 15-18 May 2011, Rio de Janeiro, Brazil, Pages: 1057 - 1060

4. M.K. Hassan, M.S. Rahaman, M. H. Chowdhury Addressing Crosstalk Issue in On-Chip Carbon Nanotube

Interconnects Using Negative Capacitance, ISCAS 2011, 15-18 May 2011, Rio de Janeiro, Brazil, pp 1407 - 1410

5. A. Roy and M.H Chowdhury, An Accurate Model for Self-Capacitance in VLSI Interconnects, 2010 IEEE

International Symposium on Circuits and Systems (ISCAS 2010), May 31-June3, 2010, Paris, France

6. P. Vora and M. H. Choudhary, Prospects and Implementation of Non-DVFS Dynamic Thermal Management

Techniques, ISCAS 2010, Paris, France, May 31- June 3, 2010

7. Hui Lin, Md. S. Rahaman and M. H Chowdhury, Microarchitecture Support for Interconnect Power-aware

Instruction Permutation, ISCAS 2010, May 31-June3, 2010, Paris, France

8. M. Rahaman and M. H Chowdhury, Interconnect Technique for Sub-Threshold Circuits using Negative Capacitance

Effect, IEEE Int. Midwest Symp on Circuits and Systems (MWSCAS 2009), Aug 2-5, 2009, Cancun, Mexico

9. S. Subash, M. Rahaman and M. H Chowdhury, Compact Model for Carbon Nanotubes Interconnects using Fourier

Series Analysis, MWSCAS 2009, August 2-5, 2009, Cancun, Mexico

10. M. Rahaman and M. H Chowdhury, Crosstalk Avoidance and Error-Correction Coding for Coupled RLC

Interconnects", IEEE International Symp. on Circuits and Systems (ISCAS 2009), Taiwan, 24-27 May 2009.

11. M. Rahaman and M. H. Chowdhury, Joint Coding for RLC Coupling-Aware on-Chip Buses, 2008 IEEE Midwest

Symp. on Circuits and Systems (MWSCAS 2008), Knoxville, TN, USA, pp 674-677, August 10-13, 2008.

12. A. Roy and M. H. Chowdhury, Impacts of Signal Slew and Skew Variations on Delay Uncertainty and Crosstalk

Noise in Coupled RLC Global Interconnects, The 15th IEEE International Conference on Electronics, Circuits and

Systems 2009 (ICECS 2009), Malta, pages 1055-1058, 31 Aug. 3 Sept. 2008,

13. M. H. Chowdhury, J. Gjanci, and P. Khaled, Innovative Power Gating for Leakage Reduction", 2008 IEEE

International Symposium on Circuits and Systems (ISCAS 2008), Seattle, USA, pp.1568-1571, May 18-21, 2008.

14. M. Rahaman and M. H. Chowdhury, Time Diversity Approach for Intra-Chip RF/Wireless Interconnect Systems",

ISCAS 2008, Seattle, WA, USA, pp 2434-2437, May 18-21, 2008.

15. A. Roy and M. H. Chowdhury, Analysis of the Impacts of Signal Rise/Fall Time and Skew Variations in Coupled-

RLC Interconnects", ISCAS 2008, Seattle, WA, USA, Page(s) 2426-2429, May 18-21, 2008.

16. J. Xu and M. H. Chowdhury, Full Waveform Accuracy to Estimate Delay in Coupled Digital Circuits", ISCAS

2008, Seattle, USA, May 18-21, 2008, pp: 3414-3417

17. J. Xu and M. H. Chowdhury, Optimization Technique for Flip-Flop Inserted Global Interconnect", ISCAS 2008,

Seattle, USA, from May 18-21, 2008, pp 3386-3389

18. J. Xu, P. Khaled, and M. H. Chowdhury, Fast bus waveform estimation at the presence of coupling noise, The 18th

ACM Great Lakes Symposium on VLSI 2008 (GLSVLSI 2008), Orlando, FL, USA, pp. 339-342, May 4-6, 2008.

19. M. Rahaman and M. Chowdhury, Improved Bit Error Rate Performance in Intra-Chip RF/Wireless Interconnect

Systems, GLSVLSI 2008, Orlando, FL, USA, May 4-6, 2008, Page(s) 303-308

20. M. H. Chowdhury, J. Gjanci, P. Khaled, Controlling Ground Bounce Noise in Power Gating Scheme for System-on-

a-Chip, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), 7-9 April 2008, France, pp.437-440

21. A. Roy and M. H. Chowdhury, Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock

Skew, 44h IEEE/ACM Design Automation Conference 2007 (DAC 2007), 4-8 June 2007, Page(s): 184 - 187

22. J. Xu, A. Roy, M. Chowdhury, "Analysis of Power Consumption and BER of Flip-flop Based Interconnect

Pipelining" IEEE/ACM Design, Automation and Test in Europe (DATE 2007), April 16-19, 2007, pp. 1218-1223

23. P. Khaled, J. Xu, and M. H. Chowdhury, Dual Diode-Vth Reduced Power Gating Structure for Better Leakage

Reduction, MWSCAS 2007, 5-8 August 2007, Montreal, Quebec, Canada, pp 1409-1412

24. A. Roy, N. Mahmoud and M. H. Chowdhury, Delay and Clock Skew Variation due to Coupling Capacitance and

Inductance ISCAS 2007, 27-30 May 2007, New Orleans, LA, USA, Page(s): 621 624

25. J. Xu, A. Roy, and M. H. Chowdhury, Power Consumption Analysis of Flip-flop Based Interconnect Pipelining,

ISCAS 2007, 27-30 May 2007, New Orleans, LA, USA, 27-30 May 2007, Page(s): 3716-3719

26. A. Roy and M. H. Chowdhury, Global Interconnect Optimization in the Presence of On-chip Inductance, ISCAS

2007, 27-30 May 2007, New Orleans, LA, USA, 27-30 May 2007, Page(s): 885-888

27. A. Roy, S. Jha and M. Chowdhury, Accurate Analysis of Switching Patterns in High Speed On-chip Global

Interconnects, The 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), 11-14

December 2007, Marrakech, Morocco, Page(s): 705-708.

28. M. Rahaman and M. H. Chowdhury, Multi-Carrier CDMA-Interconnect for Inter- and Intra-ULSI

Communications, ICECS 2007, 11-14 December 2007, Marrakech, Morocco, pp 1059-1062.

29. S. Krishnamoorthy and M. H. Chowdhury, Analysis of spatial temperature distribution in ICs, ICECS 2007, 11-14

December 2007, Marrakech, Morocco, Page(s): 1272-1275.

30. J. Xu and M. H. Chowdhury, Accurate Delay Estimation in the Presence of Coupling Noise Using Complete

Waveform Accuracy, ICECS 2007, 11-14 December 2007, Marrakech, Morocco, Page(s): 166-169.

31. V. Nigam, M. H. Chowdhury and R. Priemer, Blind Source Separation Based Compound Noise Analysis in Digital

Circuits, 2006 IEEE ISCAS, 21-24 May 2006, Island of Kos, Greece, pp 1929-1932

32. J. Xu and M. H. Chowdhury, Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining,

ICECS 2006, 10-13 December 2006, Nice, France, Page(s): 1061 - 1064

33. G. Memik, M. H. Chowdhury, A. Mallik and Y.I. Ismail, Engineering Over-Clocking: Reliability-Performance

Trade-Offs for High-Performance Register Files, Proceedings. International Conference on Dependable Systems

and Networks, 2005 (DSN 2005). 28-01 June 2005 Page(s): 770 779

34. M. H. Chowdhury and Y.I. Ismail, Analysis of coupling noise and it's scalability in dynamic circuits, IEEE Custom

Integrated Circuits Conference (CICC 2004), 3-6 Oct. 2004 Page(s): 505-508

35. C.S. Amin, M. H. Chowdhury and Y.I. Ismail, Realizable RLCK circuit crunching, 40th IEEE/ACM Design

Automation Conference (DAC 2003), 2-6 June 2003 Page(s): 226 - 231

36. M. H. Chowdhury, C.S. Amin and Y.I. Ismail, C.V. Kashyap, B.L. Krauter, Realizable reduction of RLC circuits

using node elimination, ISCAS 2003, 25-28 May 2003, Bangkok, Thailand, Page(s): 494 - 497

37. M. H. Chowdhury, Y.I Ismail, C.V Kashyap and,.; B. L. Krauter, Performance analysis of deep sub micron VLSI circuits

in the presence of self and mutual inductance, 2002 IEEE International Symp. on Circuits and Systems (ISCAS 2002),

26-29 May 2002, Scottsdale, Arizona, USA, Pages: 197-200.

38. S. Subash, M. Rahaman and M. H Chowdhury, Impact of CNT Arrangement on Capacitance and Inductance in Mixed

Bundles, IEEE 12th International Symposium on Integrated (ISIC2009), 14-16 December 2009, Singapore.

39. S. Subash and M. H Chowdhury, High Efficiency Carbon Nanotube Based Solar Cells for Electronics Devices,

ISIC2009, 14-16 December, 2009, Singapore

40. M. Rahaman and M. Chowdhury, Hybrid Bus-Invert Coding for RLC Coupling-Aware On-Chip Buses, The IEEE

CCECE'08: Symposium on Circuits, Devices and Systems, Niagara Falls, Canada, May 4-7, 2008, Pages 1161-1164

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