Engineer Software

********@***.*** Ph: +* -217-***-****

Harish Sukhwani

http://www-scf.usc.edu/~sukhwani/ 225 Mabley Pl., Cary,NC 27519

WORK EXPERIENCE

June 10 Present

Software Engineer II, Caching Services Engineering, Cisco Systems.

Developed Phy Driver (Marvell, Broadcom) for IOM card of a WAN Optimization product.

Designed Ethernet Monitor component of Platform Resource manager application.

Implemented Manufacturing diagnostics for Memory / Ethernet components.

Fall 09, Spring 10

Senior Grader, Operating Systems (CSCI 402) Prof. Michael Crowley

Design and Grade programming assignments, conducting Office hours to help students with OS theoretical concepts.

June 07 July 08

Tata TeleServices Ltd. (TTSL) Jr. Engineer in Network and Technology Dept. (NOC), Mumbai, India

Configuration of Ericsson AXE810 Switches (CDMA). Taking ISUP, SS7 protocol traces for call failures of customers.

July 06 May 07

Bhabha Atomic Research Centre (BARC) Project Trainee, Mumbai, using Analog DSP 21062

Developed a program for effective real-time compression of Magnetic Flux Leakage (MFL) data using discrete

wavelet transform (DWT) technique for Instrumented Pipeline Inspection Gauge (IPIG).

EDUCATION

University of Southern California (USC), USA May 10

Masters of Science in Electrical Engineering Computer Networks (GPA: 3.80 / 4.0)

Relevant Coursework

Computer Science : Operating Systems, Analysis of Algorithms, Computer Communications

Computer Networks (EE): Broadband Network Architecture, Design and Analysis of Computer Networks

Computer Architecture : Computer Systems Organization, Computer Systems Architecture, Digital System Design using VHDL

University of Mumbai (T.S.E.C.), India June 07

Bachelors of Engineering (B.E.) in Electronics and Telecommunication Engineering (First Class with Distinction)

Relevant Coursework

Microcontrollers and Embedded Systems, Real Time Operating Systems

NETWORK AND SYSTEMS PROJECTS

Rearrangement Scheme for Virtual Output Queued Switches : Using C, C++ Fall 09

Analyzed a 4x4 VOQ switch with a new load sharing mechanism with neighboring input queues for Poisson arriving

traffic, resulting in lower blocking probabilities or lower frame length for same Pb.

Simulated the switch using multi-threaded C program, Poisson arrival process and maximum bipartite matching

scheduling scheme, and calculated the blocking probability to support the above analysis.

Delay Tolerant Network architecture simulation : Using C, C++, UNIX sockets, BGP, RIP, TCP/IP Spring 09

Implemented multi-threaded nodes in client-server model and sorted Queue structure for message storage.

Designed a Distance Vector based routing algorithm to find shortest paths between nodes.

Implemented asynchronous message forwarding between nodes using ACKs and ReTx timeouts (ARQ).

Operating System development in Nachos : Using C, C++, Solaris Fall 08

Implemented algorithms for kernel tasks like Thread Synchronization primitives, Mutual Exclusion (local and

distributed), Threads and Process Management, System calls, Memory management, Virtual memory.

Implemented distributed networking using RPC s and full redundant server architecture to handle various clients.

Nachos-like OS on Freescale C, Prof. Michael Crowley, Prof. Mark Redekopp, using I2C, USB, Ethernet Fall 09, Spring 10

Experiment with features / applications of Coldfire microcontroller, demonstrate to team-members.

Study Ethernet controller driver and design future OS projects for class 402, based on C platform.

COMPUTER ARCHITECTURE PROJECTS

Tomasulo out-of-order architecture with Reorder buffer : Using VHDL, Xilinx 10.1, JTAG, ModelSim Summer 09

Designed components for the Tomasulo architecture using VHDL, wrote Test benches and simulated using

ModelSim, and implemented it on the Nexys2 board using Xilinx 10.1 tool kit.

Analysis and Design improvement on an out-of-order processor using Simple Scalar, RealEstimator, CACTI Spring 09

Analyzed the CPI and MIPS for processors with different instruction execution widths.

Designed the new processor by modifying the sizes and counts of Cache, Set associativity, Instruction widths, ALU, to

achieve highest possible MIPS rate.

SKILLS

Languages C, C++, MATLAB, Perl, VHDL, Verilog, x86, MIPS

Network Tools WireShark, Opnet, tcpdump.

ACHIEVEMENTS / ACTIVITIES

Academic Achievement Award for International Students at University of Southern California.

Secured 98.3 percentile in Graduate Aptitude Test in Engineering (GATE 07) in Electronics and Communication (EC) branch..

Completed Curriculum for Living at Landmark Education.

Webmaster and Chief Technical Officer of IEEE-TSEC Student branch for the year 2005, 2006.

Runners Up prize at world level in IEEE International Student Branch Website Design Contest 2005.

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