Computer Systems
Resume:
Onur Mutlu
**** ****** ***., *********** **** A**5, Pittsburgh, PA 15213 Work Phone: 412-***-****
Email: abqb11@r.postjobfree.com
http://www.ece.cmu.edu/ omutlu
Research and Teaching Interests
Computer architecture and systems. Memory systems. Multi/many-core systems. Scalable, QoS-aware, latency-tolerant systems.
Computer architectures for secure and robust operating systems (OS). OS/architecture interaction.
Architectural support for safe/managed/parallel programming languages (PL) and programmer productivity. PL/architecture interaction.
Fault tolerant and bug-tolerant architectures. Dependable systems.
System-wide resource management and QoS, especially in multi-core and multithreaded systems.
Novel computer architectures for health, biological, medical, and bioinformatics applications.
Education
University of Texas at Austin Ph.D., Computer Engineering, August 2006
September 2000 - August 2006 Dissertation Title: Ef cient Runahead Execution Processors
Nominated for the ACM Doctoral Dissertation Award by UT-Austin
M.S.E., Computer Engineering, May 2002
University of Michigan, Ann Arbor B.S.E., summa cum laude, Computer Engineering, August 2000
September 1997 - August 2000 B.S., with highest distinction, Psychology, August 2000
Professional Work Experience
Carnegie Mellon University, Dept. of Electrical and Computer Engineering, Assistant Professor, January 2009 - Present
Carnegie Mellon University, Dept. of Computer Science, Courtesy Assistant Professor, January 2009 - Present
Microsoft Research, Computer Architecture Group (Redmond, WA), Researcher, August 2006 - January 2009
University of Texas at Austin, Dept. of Electrical and Computer Engineering, Research and Teaching Assistant, August 2000 - August 2006
Advanced Micro Devices, Architecture/Performance Modeling Group (Sunnyvale, CA), Co-op Engineer, May August 2005
Advanced Micro Devices, Architecture/Performance Modeling Group (Sunnyvale, CA), Co-op Engineer, May August 2004
Intel Corporation, Desktop Platforms Group (Hillsboro, OR), Graduate Technical Intern, May August 2003
Intel Corporation, Microprocessor Research Labs (Hillsboro, OR), Graduate Technical Intern, May August 2002
Intel Corporation, Desktop Platforms Group (Hillsboro, OR), Graduate Technical Intern, May August 2001
Honors, Awards and Achievements
Intel Early Career Faculty Honor Program Award, 2012
Carnegie Mellon University College of Engineering George Tallman Ladd Research Award, 2012
IEEE Computer Society Technical Committee on Computer Architecture Young Computer Architect Award, 2011
IBM Faculty Partnership Award, 2012
Hewlett-Packard Laboratories Innovation Research Program Award, 2012
Nvidia CUDA Center of Excellence Award, 2012 (with multiple CMU Faculty members)
Best paper award at ICCD 2012 (Computer Systems and Applications Track)
Row Buffer Locality Aware Caching Policies for Hybrid Memories
Best paper award at ASPLOS 2010
Fairness via Source Throttling: A Con gurable and High-Performance Fairness Substrate for Multi-Core Memory Systems
Best paper award at VTS 2010 (awarded in 2011)
Concurrent Autonomous Self-Test for Uncore Components in System-on-Chips
One paper (of 12 total) selected for IEEE Micro s Top Picks from Computer Architecture Conferences, 2011
Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees
Three papers (of 11 total) selected for IEEE Micro s Top Picks from Computer Architecture Conferences, 2010
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
Aergia: Exploiting Packet Latency Slack in On-Chip Networks
Data Marshaling for Multi-core Architectures
Two papers (of 13 total) selected for IEEE Micro s Top Picks from Computer Architecture Conferences, 2009
Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures
Architecting Phase Change Memory as a Scalable DRAM Alternative
One paper (of 12 total) selected for IEEE Micro s Top Picks from Computer Architecture Conferences, 2008
Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers
One paper (of 11 total) selected for IEEE Micro s Top Picks from Computer Architecture Conferences, 2006
Diverge-Merge Processor (DMP): Generalized and Energy-Ef cient Dynamic Predication
Two papers (of 13 total) selected for IEEE Micro s Top Picks from Computer Architecture Conferences, 2005
Ef cient Runahead Execution: Power-ef cient Memory Latency Tolerance
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution
One paper (of 15 total) selected for IEEE Micro s Top Picks from Computer Architecture Conferences, 2003
Runahead Execution: An Effective Alternative to Large Instruction Windows
One paper selected for CACM s Research Highlights, 2009
Architecting Phase Change Memory as a Scalable DRAM Alternative
Best Paper Session at HPCA 2010: ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers
Best Paper Session at HPCA 2009: Techniques for Bandwidth-Ef cient Prefetching of Linked Data Structures in Hybrid Prefetching Systems
Best paper award nominations at NOCS 2012, HPCA 2010, HPCA 2009, HPCA 2007, MICRO 2006, and MICRO 2005 conferences
Selected to the ISCA and MICRO Halls of Fame, 2009
NSF CAREER Award, 2010 (QoS-Aware, High-Performance, and Scalable Many-Core Memory Systems)
Microsoft Gold Star Award, 2008
PhD Dissertation nominated by UT-Austin for the ACM Doctoral Dissertation Award, 2006
University Co-op/George H. Mitchell Award for Excellence in Graduate Research (Awarded to 6 out of 271 nominees at UT-Austin), 2005
Intel Foundation Ph.D. Fellowship, 2004
University of Texas Graduate School Continuing Fellowship, 2003
University of Michigan EECS Dept. Summer Research Fellowship, 1999, 2000
University of Michigan EECS Dept. William Harvey Seeley Award (money award given to the top undergraduate junior), 1999
University of Michigan Branstrom Freshman Prize, 1998
Publications
(Please visit http://www.ece.cmu.edu/ omutlu/projects.htm for electronic copies.)
Refereed Conference (and Major Workshop) Publications
1. Emre Kultursay, Mahmut Kandemir, Anand Sivasubramaniam, Onur Mutlu, Evaluating STT-RAM Technology as an Energy Ef cient
Main Memory Alternative, Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS),
Austin, TX, April 2013.
2. Yu Cai, Eric F. Haratsch, Onur Mutlu, Ken Mai, Threshold Voltage Distribution in MLC NAND Flash: Characterization, Analysis and
Modeling, Proceedings of the Design, Automation, and Test in Europe Conference (DATE), Grenoble, France, March 2013.
3. Adwait Jog, Onur Kayiran, Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar K.
Iyer, and Chita R. Das, OWL: FOcused Thread-array aWare ScheduLing for Enhanced Performance in GPGPUs, Proceedings of the 18th
ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Houston, TX,
March 2013.
4. Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu, Tiered-Latency DRAM: A Low Latency
and Low Cost DRAM Architecture, Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture
(HPCA), Shenzhen, China, February 2013.
5. Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu, MISE: Providing Performance Predictability and Improv-
ing Fairness in Shared Main Memory Systems, Proceedings of the 19th IEEE International Symposium on High Performance Computer
Architecture (HPCA), Shenzhen, China, February 2013.
6. Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi, Application-to-Core Mapping Policies to Reduce
Memory System Interference in Multi-Core Systems, Proceedings of the 19th IEEE International Symposium on High Performance
Computer Architecture (HPCA), Shenzhen, China, February 2013.
7. Hongyi Xin, Donghyuk Lee, Farhad Hormozdiari, Samihan Yedkar, Onur Mutlu, Can Alkan, Accelerating Read Mapping with FastHASH,
Proceedings of the 11th Asia Paci c Bioinformatics Conference (APBC), Vancouver, BC, Canada, January 2013.
8. Kevin Chang, Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu, HAT: Heterogeneous Adaptive Throttling: for On-Chip Networks,
Proceedings of the 24th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), New
York, NY, October 2012.
9. HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, Onur Mutlu, A High-Performance and Energy-Ef cient Row
Buffer Locality-Aware Caching Policy for Hybrid Memories, Proceedings of the 30th IEEE International Conference on Computer Design
(ICCD), Montreal, Quebec, Canada, September 2012. Best Paper Award (Computer Systems and Applications Track).
10. Yu Cai, Gulay Yalcin, Onur Mutlu, Eric Haratsch, Adrian Cristal, Osman Unsal, Ken Mai, Flash Correct-and-Refresh: Retention-Aware
Error Management for Increased Flash Memory Lifetime, Proceedings of the 30th IEEE International Conference on Computer Design
(ICCD), Montreal, Quebec, Canada, September 2012.
11. Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, Todd C. Mowry, The Evicted-Address Filter: A Uni ed Mechanism to Address Both
Cache Pollution and Thrashing, Proceedings of the 21st ACM International Conference on Parallel Architectures and Compilation Tech-
niques (PACT), Minneapolis, MN, September 2012.
12. Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu, Philip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Base-Delta-Immediate
Compression: A Practical Data Compression Mechanism for On-Chip Caches, Proceedings of the 21st ACM International Conference on
Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, September 2012.
13. George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu, Srinivasan Seshan, On-Chip Networks from a Networking Perspective:
Congestion and Scalability in Many-core Interconnects, Proceedings of the 2012 ACM SIGCOMM Conference (SIGCOMM), Helsinki,
Finland, August 2012.
14. Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu, RAIDR: Retention-Aware Intelligent DRAM Refresh, Proceedings of the 39th
IEEE/ACM International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.
15. Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu, A Case for Exploiting Subarray-Level Parallelism (SALP) in
DRAM, Proceedings of the 39th IEEE/ACM International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.
16. Rachata Ausavarungnirun, Kevin Chang, Lavanya Subramanian, Gabriel Loh, Onur Mutlu, Staged Memory Scheduling: Achieving High
Performance and Scalability in Heterogeneous Systems, Proceedings of the 39th IEEE/ACM International Symposium on Computer Ar-
chitecture (ISCA), Portland, OR, June 2012.
17. Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu, MinBD: Minimally-Buffered De ec-
tion Routing for Energy-Ef cient Interconnect, Proceedings of the 6th International Networks-On-Chip Symposium (NOCS), Lyngby,
Denmark, May 2012. One of the 5 papers nominated for the Best Paper Award by the Program Committee
18. Yu Cai, Eric F. Haratsch, Onur Mutlu, Ken Mai, Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and
Analysis, Proceedings Design, Automation, and Test in Europe Conference (DATE), Dresden, Germany, March 2012.
19. Jose A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt, Bottleneck Identi cation and Scheduling in Multithreaded Applications,
Proceedings of the 17th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
(ASPLOS), London, UK, March 2012.
20. Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, Thomas Moscibroda, Reducing Memory Interference
in Multicore Systems via Application-Aware Memory Channel Partitioning, Proceedings of the 44th IEEE/ACM International Symposium
on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011.
21. Eiman Ebrahimi, Rustam Miftakhutdinov, Chang Joo Lee, Onur Mutlu, Chris Fallin, Yale N. Patt, Managing Inter-thread Memory System
Interference for Parallel Applications, Proceedings of the 44th IEEE/ACM International Symposium on Microarchitecture (MICRO), Porto
Alegre, Brazil, December 2011.
22. Veynu Narasiman, Chang Joo Lee, Michael Shebanow, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt, Improving GPU Performance
via Large Warps and Two-Level Warp Scheduling, Proceedings of the 44th IEEE/ACM International Symposium on Microarchitecture
(MICRO), Porto Alegre, Brazil, December 2011.
23. Boris Grot, Joel Hestness, Steve Keckler, Onur Mutlu, Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and
Service Guarantees, Proceedings of the 38th IEEE/ACM International Symposium on Computer Architecture (ISCA), San Jose, CA, June
2011. One of the 12 papers of 2011 selected as Top Picks by IEEE Micro
24. Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt, Prefetch-Aware Shared-Resource Management for Multi-Core Systems,
Proceedings of the 38th IEEE/ACM International Symposium on Computer Architecture (ISCA), San Jose, CA, June 2011.
25. Howard David, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, Onur Mutlu, Memory Power Management via Dynamic Voltage/Frequency
Scaling, Proceedings of the 8th IEEE International Conference on Autonomic Computing (ICAC), Karlsruhe, Germany, June 2011.
26. Michael Papamichael, James Hoe, Onur Mutlu, FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling
in Full-System Simulations, Proceedings of the 5th International Networks-On-Chip Symposium (NOCS), Pittsburgh, PA, May 2011.
27. Chris Fallin, Chris Craik, Onur Mutlu, CHIPPER: A Low-complexity Bufferless De ection Router, Proceedings of the 17th IEEE Inter-
national Symposium on High Performance Computer Architecture (HPCA), San Antonio, TX, February 2011.
28. Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter, Thread Cluster Memory Scheduling: Exploiting Differences
in Memory Access Behavior, Proceedings of the 43rd IEEE/ACM International Symposium on Microarchitecture (MICRO), Atlanta, GA,
December 2010. One of the 11 papers of 2010 selected as Top Picks by IEEE Micro
29. George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu, Next Generation On-Chip Networks: What Kind of Congestion Control
Do We Need?, Proceedings of the 9th ACM Workshop on Hot Topics in Networks (HotNETS), Monterey, CA, October 2010.
30. Tanausu Ramirez, Alex Pajuelo, Oliverio Santana, Onur Mutlu, and Mateo Valero, Ef cient Runahead Threads, Proceedings of the 19th
ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Vienna, Austria, September 2010.
31. Reetuparna Das, Onur Mutlu, Thomas Moscibroda, and Chita R. Das, Aergia: Exploiting Packet Latency Slack in On-Chip Networks,
Proceedings of the 37th IEEE/ACM International Symposium on Computer Architecture (ISCA), St. Malo, France, June 2010. One of the
11 papers of 2010 selected as Top Picks by IEEE Micro
32. M. Aater Suleman, Onur Mutlu, Jose A. Joao, Khubaib, and Yale N. Patt, Data Marshaling for Multi-core Architectures, Proceedings of
the 37th IEEE/ACM International Symposium on Computer Architecture (ISCA), St. Malo, France, June 2010. One of the 11 papers of
2010 selected as Top Picks by IEEE Micro
33. Boris Grot, Steve Keckler, and Onur Mutlu, Topology-aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors, Pro-
ceedings of the 6th Annual Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), in conjunction
with the 37th International Symposium on Computer Architecture, St. Malo, France, June 2010.
34. Paul Bogdan, Miray Kas, Radu Marculescu, and Onur Mutlu, QuaLe: A Quantum-Leap Inspired Model for Non-Stationary Analysis of
NoC Traf c in Multi-Processor Platforms, Proceedings of the 4th International Networks-On-Chip Symposium (NOCS), May 2010.
35. Yanjing Li, Onur Mutlu, Donald S. Gardner, and Subhasish Mitra, Concurrent Autonomous Self-Test for Uncore Components in System-
on-Chips Proceedings of the 28th IEEE VLSI Test Symposium (VTS), Santa Cruz, CA, April 2010.
36. Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt, Fairness via Source Throttling: A Con gurable and High-Performance
Fairness Substrate for Multi-Core Memory Systems, Proceedings of the 15th ACM International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS), Pittsburgh, PA, March 2010. Best Paper Award.
37. Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter, ATLAS: A Scalable and High-Performance Scheduling Algorithm
for Multiple Memory Controllers, Proceedings of the 16th IEEE International Conference on High Performance Computer Architecture
(HPCA), Bangalore, India, January 2010. Best Paper Session. One of the 4 papers nominated for the Best Paper Award by the
Program Committee.
38. Reetuparna Das, Onur Mutlu, Thomas Moscibroda, and Chita R. Das, Application-Aware Prioritization Mechanisms for On-Chip Net-
works, Proceedings of the 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO), New York, NY, pp. 280-291,
December 2009.
39. Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, and Yale N. Patt, Coordinated Control of Multiple Prefetchers in Multi-Core Systems,
Proceedings of the 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO), New York, NY, pp. 316-326, December
2009.
40. Boris Grot, Steve Keckler, and Onur Mutlu, Preemptive Virtual Clock: A Flexible, Ef cient, and Cost-effective QOS Scheme for
Networks-on-Chip, Proceedings of the 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO), New York, NY, pp.
268-279, December 2009.
41. Chang Joo Lee, Veynu Narasiman, Onur Mutlu, and Yale N. Patt, Improving Memory Bank-Level Parallelism in the Presence of Prefetch-
ing, Proceedings of the 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO), New York, NY, pp. 327-336, Decem-
ber 2009.
42. Yanjing Li, Onur Mutlu, and Subhasish Mitra, Operating System Scheduling for Ef cient Online Self-Test in Robust Systems, Pro-
ceedings of the 2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, pp. 201-208, November
2009.
43. Thomas Moscibroda and Onur Mutlu, A Case for Bufferless Routing in On-Chip Networks, Proceedings of the 36th IEEE/ACM Interna-
tional Symposium on Computer Architecture (ISCA), pp. 196-207, Austin, TX, June 2009.
44. Jos A. Joao, Onur Mutlu, and Yale N. Patt, Flexible Reference Counting Based Hardware Acceleration for Garbage Collection, Pro-
e
ceedings of the 36th IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 418-428, Austin, TX, June 2009.
45. Benjamin Lee, Engin Ipek, Onur Mutlu, and Doug Burger, Architecting Phase Change Memory as a Scalable DRAM Alternative, Pro-
ceedings of the 36th IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 2-13, Austin, TX, June 2009. One of the
13 papers of 2009 selected as Top Picks by IEEE Micro. Opening Paper of the Conference. Selected for publication in CACM
Research Highlights.
46. M. Aater Suleman, Onur Mutlu, Moinuddin Qureshi, Yale N. Patt, Accelerating Critical Section Execution with Asymmetric Multi-
Core Architectures, Proceedings of the 14th ACM International Conference on Architectural Support for Programming Languages and
Operating Systems (ASPLOS), pp. 253-264, Washington, DC, March 2009. One of the 13 papers of 2009 selected as Top Picks by
IEEE Micro
47. Eiman Ebrahimi, Onur Mutlu, Yale N. Patt, Techniques for Bandwidth-Ef cient Prefetching of Linked Data Structures in Hybrid Prefetch-
ing Systems, Proceedings of the 15th IEEE International Conference on High Performance Computer Architecture (HPCA), pp. 7-17,
Raleigh, NC, February 2009. Best Paper Session. One of the 3 papers nominated for the Best Paper Award by the Program Com-
mittee
48. Boris Grot, Joel Hestness, Steve Keckler, Onur Mutlu, Express Cube Topologies for On-Chip Interconnects, Proceedings of the 15th
IEEE International Conference on High Performance Computer Architecture (HPCA), pp. 163-174, Raleigh, NC, February 2009.
49. Kypros Constantinides, Onur Mutlu, Todd Austin, Online Design Bug Detection: RTL Analysis, Flexible Mechanisms, and Evaluation,
Proceedings of the 41st IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 282-293, Lake Como, Italy, November
2008.
50. Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt, Prefetch Aware DRAM Controllers, Proceedings of the 41st IEEE/ACM
International Symposium on Microarchitecture (MICRO), pp. 200-209, Lake Como, Italy, November 2008.
51. Thomas Moscibroda and Onur Mutlu, Distributed Order Scheduling and its Application to Multi-Core DRAM Controllers, Proceedings
of the 27th Annual ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing (PODC), pp. 365-374, Toronto, Canada,
August 2008.
52. Onur Mutlu and Thomas Moscibroda, Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM
Systems, Proceedings of the 35th IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 63-74, Beijing, China, June
2008. One of the 12 papers of 2008 selected as Top Picks by IEEE Micro
53. Engin Ipek, Onur Mutlu, Jos F. Mart nez, Rich Caruana, Self-Optimizing Memory Controllers: A Reinforcement Learning Approach,
e
Proceedings of the 35th IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 39-50, Beijing, China, June 2008.
54. Jos A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt, Improving the Performance of Object-Oriented Languages with
e
Dynamic Predication of Indirect Jumps, Proceedings of the 13th ACM International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS), pp. 80-90, Seattle, WA, March 2008.
55. Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt, Performance-aware Speculation Control using Wrong Path Usefulness Predic-
tion, Proceedings of the 14th IEEE International Conference on High Performance Computer Architecture (HPCA), pp. 39-49, Salt Lake
City, UT, February 2008.
56. Onur Mutlu and Thomas Moscibroda, Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, Proceedings of the 40th
IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 146-158, Chicago, IL, December 2007.
57. Kypros Constantinides, Onur Mutlu, Todd Austin, and Valeria Bertacco, Software-Based Online Detection of Hardware Defects: Mech-
anisms, Architectural Support, and Evaluation, Proceedings of the 40th IEEE/ACM International Symposium on Microarchitecture (MI-
CRO), pp. 97-108, Chicago, IL, December 2007.
58. Thomas Moscibroda and Onur Mutlu, Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems, Proceedings of
the 16th USENIX Security Symposium (USENIX SECURITY), pp. 257-274, Boston, MA, August 2007.
59. Hyesoon Kim, Jos A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert S. Cohn, VPC Prediction: Reducing the Cost of Indirect
e
Branches via Hardware-based Dynamic Devirtualization, Proceedings of the 34th IEEE/ACM International Symposium on Computer
Architecture (ISCA), pp. 424-435, San Diego, CA, June 2007.
60. Hyesoon Kim, Jos A. Joao, Onur Mutlu, Yale N. Patt, Pro le-assisted Compiler Support for Dynamic Predication in Diverge-Merge
e
Processors, Proceedings of the 5th Annual International Symposium on Code Generation and Optimization (CGO), pp. 367-378, San
Jose, CA, March 2007.
61. Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt, Feedback Directed Prefetching: Improving the Performance and Bandwidth-
Ef ciency of Hardware Prefetchers, Proceedings of the 13th IEEE International Conference on High Performance Computer Architecture
(HPCA), pp. 63-74, Phoenix, AZ, February 2007. One of the 5 papers nominated for the Best Paper Award by the Program Committee
62. Hyesoon Kim, Jos Joao, Onur Mutlu, Yale N. Patt, Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex
e
Control-Flow Graphs Based on Frequently Executed Paths, Proceedings of the 38th IEEE/ACM Annual International Symposium on
Microarchitecture (MICRO), pp. 53-64, Orlando, FL, December 2006. One of the 11 papers of 2006 selected as Top Picks by IEEE
Micro
63. Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt, A Case for MLP-Aware Cache Replacement, Proceedings of the 33rd
IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 167-177, Boston, MA, USA, June 2006.
64. Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt, 2D-Pro ling: Detecting Input-Dependent Branches with a Single Input Data
Set, Proceedings of the 4th Annual International Symposium on Code Generation and Optimization (CGO), pp. 159-169, New York, NY,
USA, March 2006.
65. Onur Mutlu, Hyesoon Kim, Yale N. Patt, Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution
by Exploiting Regular Memory Allocation Patterns, Proceedings of the 38th IEEE/ACM Annual International Symposium on Microarchi-
tecture (MICRO), pp. 233-244, Barcelona, Spain, November 2005. One of the 5 papers nominated for the Best Paper Award by the
Program Committee
66. Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt, Wish Branches: Combining Conditional Branching and Predication for Adaptive
Predicated Execution, Proceedings of the 38th IEEE/ACM Annual International Symposium on Microarchitecture (MICRO), pp. 43-54,
Barcelona, Spain, November 2005. One of the 13 papers of 2005 selected as Top Picks by IEEE Micro
67. Onur Mutlu, Hyesoon Kim, Yale N. Patt, Techniques for Ef cient Processing in Runahead Execution Engines, Proceedings of the 32nd
IEEE/ACM International Symposium on Computer Architecture (ISCA), pp. 370-381, Madison, WI, USA, June 2005. One of the 13
papers of 2005 selected as Top Picks by IEEE Micro
68. Moinuddin K. Qureshi, Onur Mutlu, and Yale N. Patt, Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance
in Microprocessors, Proceedings of the 2005 IEEE International Conference on Dependable Systems and Networks (DSN), pp. 434-443,
Yokohama, Japan, June 2005.
69. David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt, Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for
Early Misprediction Detection and Recovery, Proceedings of the 37th IEEE/ACM Annual International Symposium on Microarchitecture
(MICRO), pp. 119-128, Portland, OR, USA, December 2004.
70. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt, Cache Filtering Techniques to Reduce the Negative Impact of Useless Spec-
ulative Memory References on Processor Performance, Proceedings of the 16th IEEE International Symposium on Computer Architecture
and High Performance Computing (SBAC-PAD), pp. 2-9, Foz do Iguacu, Brazil, October 2004. Opening Paper of the Conference.
71. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt, Understanding The Effects of Wrong-Path Memory References on Pro-
cessor Performance, Proceedings of the 3rd ACM Workshop on Memory Performance Issues (WMPI), in conjunction with the 31st Inter-
national Symposium on Computer Architecture, pp. 56-64, Munchen, Germany, June 2004.
72. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt, Runahead Execution: An Alternative to Very Large Instruction Windows for
Out-of-order Processors, Proceedings of the 9th IEEE International Conference on High Performance Computer Architecture (HPCA),
pp. 129-140, Anaheim, CA, USA, February 2003. One of the 15 papers of 2003 selected as Top Picks by IEEE Micro
Refereed Journal Publications
73. Boris Grot, Joel Hestness, Stephen W. Keckler, and Onur Mutlu, A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips, IEEE
Micro, Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 32 (3), May/June 2012.
74. Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt, Fairness via Source Throttling: A Con gurable and High-Performance
Fairness Substrate for Multi-Core Memory Systems, to appear in ACM Transactions on Computer Systems, May 2012.
75. Justin Meza, Jichuan Chang, HanBin Yoon, Onur Mutlu, Parthasarathy Ranganathan, Enabling Ef cient and Scalable Hybrid Memories
Using Fine-Granularity DRAM Cache Management, IEEE Computer Architecture Letters, February 2012.
76. Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt, Prefetch-Aware Memory Controllers, IEEE Transactions on Comput-
ers, vol. 60 (10), pp. 1406-1430, October 2011.
77. Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter, Thread Cluster Memory Scheduling, IEEE Micro, Special
Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 31 (1), January/February 2011.
78. Reetuparna Das, Onur Mutlu, Thomas Moscibroda, and Chita R. Das, Aergia: A Network-On-Chip Exploiting Packet Latency Slack,
IEEE Micro, Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 31 (1), January/February 2011.
79. M. Aater Suleman, Onur Mutlu, Jose A. Joao, Khubaib, and Yale N. Patt, Data Marshaling for Multi-core Systems, IEEE Micro, Special
Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 31 (1), January/February 2011.
80. Benjamin Lee, Engin Ipek, Onur Mutlu, Doug Burger, Phase Change Memory Architecture and the Quest for Scalability, Communica-
tions of the ACM (CACM), Research Highlight, vol. 53 (7), pp. 99-106, July 2010.
81. M. Aater Suleman, Onur Mutlu, Moinuddin Qureshi, Yale N. Patt, Accelerating Critical Section Execution with Asymmetric Multi-Core
Architectures, IEEE Micro, Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 30 (1), pp. 131-141,
January/February 2010.
82. Benjamin Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger, Phase Change Technology and the
Future of Main Memory, IEEE Micro, Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 30 (1),
pp. 60-70, January/February 2010.
83. Can Alkan, Jeffrey M. Kidd, Tomas Marques-Bonet, Gozde Aksay, Francesca Antonacci, Fereydoun Hormozdiari, Jacob O. Kitzman,
Carl Baker, Maika Malig, Onur Mutlu, S. Cenk Sahinalp, Richard A. Gibbs, Evan E. Eichler, Personalized Copy-Number and Segmental
Duplication Maps using Next-Generation Sequencing, Nature Genetics, [Epub: August 30], vol. 41 (10), pp. 1061-1067, October 2009.
84. Hyesoon Kim, Jos A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert S. Cohn, Virtual Program Counter (VPC) Prediction: Very
e
Low-Cost Indirect Branch Prediction using Conditional Branch Prediction Hardware, IEEE Transactions on Computers (TC), vol. 58
(9), pp. 1153-1170, September 2009. Online featured article.
85. Kypros Constantinides, Onur Mutlu, Todd Austin, and Valeria Bertacco, A Flexible Software-Based Framework for Online Detection of
Hardware Defects, IEEE Transactions on Computers (TC), vol. 58 (8), pp. 1063-1079, August 2009.
86. Onur Mutlu and Thomas Moscibroda, Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers,
IEEE Micro, Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 28(1), January/February 2009.
87. Jos A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt, Dynamic Predication of Indirect Jumps, IEEE Computer Architecture Letters
e
(CAL), vol. 6, May 2007.
88. Hyesoon Kim, Jos A. Joao, Onur Mutlu, Yale N. Patt, Diverge-Merge Processor: Generalized and Energy-Ef cient Dynamic Pred-
e
ication, IEEE Micro, Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 27(1), pp. 94-104,
January/February 2007.
89. Onur Mutlu, Hyesoon Kim, Yale N. Patt, Address-Value Delta (AVD) Prediction: A Hardware Technique for Ef ciently Parallelizing
Dependent Cache Misses, IEEE Transactions on Computers (TC), vol. 55 (12), pp. 1491-1508, December 2006. Featured article.
90. Onur Mutlu, Hyesoon Kim, Yale N. Patt, Ef cient Runahead Execution: Power-Ef cient Memory Latency Tolerance, IEEE Micro,
Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 26(1), pp. 10-20, January/February 2006.
91. Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt, Wish Branches: Enabling Adaptive and Aggressive Predicated Execution, IEEE
Micro, Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 26(1), pp. 48-58, January/February 2006.
92. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt, An Analysis of the Performance Impact of Wrong-Path Memory References
on Out-of-Order and Runahead Execution Processors, IEEE Transactions on Computers (TC), vol. 54 (12), pp. 1556-1571, December
2005.
93. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt, Using the First-Level Caches as Filters to Reduce the Pollution Caused by
Speculative Memory References, International Journal of Parallel Programming (IJPP), vol. 33 (5), pp. 529-559, October 2005.
94. Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt, On Reusing the Results of Pre-Executed Instructions in a Runahead Execution
Processor, IEEE Computer Architecture Letters (CAL), vol. 4, January 2005.
95. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt, Runahead Execution: An Effective Alternative to Large Instruction Windows,
IEEE Micro, Special Issue: Top Picks from Computer Architecture Conferences (TOP PICKS), vol. 23(6), pp. 20-25, Novem-
ber/December 2003.
Editorial Articles
96. Yale N. Patt, Onur Mutlu, Guest Editors Introduction: Top Picks, IEEE Micro, Special Issue (IEEE MICRO), vol. 31(1), Jan-
uary/February 2011.
97. Sangyeun Cho, Tao Li, Onur Mutlu, Interaction of Many-core Computer Architecture and Operating Systems: Guest Editors Introduc-
tion, IEEE Micro, Special Issue (IEEE MICRO), vol. 28(3), pp. 2-5, May/June 2008.
Signi cant Abstracts and Conference Presentations
98. Justin Meza, Jing Li, Onur Mutlu, A Case for Small Row Buffers in Non-Volatile Main Memories, Short poster paper at the 30th IEEE
International Conference on Computer Design (ICCD), Montreal, Quebec, Canada, September 2012.
99. Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi, Application-to-Core Mapping Policies to Reduce
Memory Interference in Multi-Core Systems, Short poster paper at the 21st ACM International Conference on Parallel Architectures and
Compilation Techniques (PACT), Minneapolis, MN, September 2012.
100. Nachiappan C. Nachiappan, Asit K. Mishra, Mahmut Kandemir, Anand Sivasubramaniam, Onur Mutlu, Chita R. Das, Application-aware
Prefetch Prioritization in On-chip Networks, Short poster paper at the 21st ACM International Conference on Parallel Architectures and
Compilation Techniques (PACT), Minneapolis, MN, September 2012.
101. Hongyi Xin, Donghyuk Lee, Farhad Hormozdiari, Can Alkan, Onur Mutlu, FastHASH: A New GPU-friendly Algorithm for Fast and
Comprehensive Next-generation Sequence Mapping, Paci c Symposium on Biocomputing (PSB) Poster Session, Hawaii, January 2012.
Signi cant Technical Reports (otherwise unpublished)
102. Asit K. Mishra, Onur Mutlu, Chita R. Das, Design of Heterogeneous On-Chip Networks: An Application Driven Approach, SAFARI
Technical Report, TR-SAFARI-2011-010, Carnegie Mellon University, October 2011.
103. Chris Fallin, Xiangyao Yu, Greg Nazario, Onur Mutlu, A High-Performance Hierarchical Ring On-Chip Interconnect with Low-Cost
Routers, SAFARI Technical Report, TR-SAFARI-2011-007, Carnegie Mellon University, September 2011.
104. Chris Craik, Onur Mutlu, Investigating the Viability of Bufferless NoCs in Modern Chip Multi-Processor Systems, SAFARI Technical
Report, TR-SAFARI-2011-004, Carnegie Mellon University, August 2011.
105. Reetuparna Das, Onur Mutlu, Akhilesh Kumar, Mani Azimi, Application-to-Core Mapping Policies to Reduce Interference in On-Chip
Networks, SAFARI Technical Report, TR-SAFARI-2011-001, Carnegie Mellon University, May 2011.
106. Chang Joo Lee, Eiman Ebrahimi, Veynu Narasiman, Onur Mutlu, Yale N. Patt, DRAM-Aware Last-Level Cache Replacement, HPS
Technical Report, TR-HPS-2010-007, December 2010.
107. Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt, DRAM-Aware Last-Level Cache Writeback: Reducing
Write-Caused Interference in Memory Systems, HPS Technical Report, TR-HPS-2010-002, April 2010.
108. Onur Mutlu, Ef cient Runahead Execution Processors, Ph.D. Dissertation, HPS Technical Report, TR-HPS-2006-007, July 2006. Nom-
inated for the ACM Doctoral Dissertation Award by the University of Texas at Austin
Major Submissions Currently Under Review
109. Chris Fallin, Chris Craik, Onur Mutlu, CHIPPER: A Low-complexity Bufferless De ection Router, submitted to ACM Transactions on
Architecture and Code Optimization, under review since August 2011.
Patents and Invention Disclosures ( led while in Industry)
1. Thomas Moscibroda, Onur Mutlu, Bufferless Routing in On-Chip Interconnection Networks, US Patent application led January 2009.
2. Thomas Moscibroda, Onur Mutlu, Prioritization of Multiple Concurrent Threads for Scheduling Requests to Shared Memory, US Patent
application led October 2008.
3. Thomas Moscibroda, Onur Mutlu, Coordination Mechanisms among Multiple Memory Controllers for Reducing Energy Consumption,
US Patent application led March 2008.
4. Thomas Moscibroda, Onur Mutlu, Controlling Interference in Shared DRAM Systems using Batch Scheduling, US Patent Application
led February 2008.
5. Onur Mutlu, Jos A. Joao, Feedback Mechanism for Dynamic Predication of Indirect Jumps, US Patent Application led December
e
2007.
6. Jos A. Joao, Onur Mutlu, Target-Frequency based Indirect Jump Prediction for High-Performance Processors, US Patent Application
e
led December 2007.
7. Onur Mutlu, Thomas Moscibroda, A Software-Con gurable and Stall-Time Fair Memory Access Scheduling Mechanism for Shared
Memory Systems, US Patent Application led November 2007.
8. Thomas Moscibroda, Onur Mutlu, Multi-level DRAM Controller to Manage Access to DRAM, US Patent Application led August 2007.
9. Onur Mutlu, Thomas Moscibroda, Parallelism-Aware Memory Request Scheduling in Shared Memory Controllers, US Patent Applica-
tion led August 2007.
10. Thomas Moscibroda, Onur Mutlu, Fairness in Memory Systems, US Patent Application led July 2007.
11. Jared Stark, Chris Wilkerson, Onur Mutlu, Apparatus for Memory Communication During Runahead Execution, US Patent Application
led December 2002.
12. Eric Sprangle, Onur Mutlu, Method and Apparatus to Control Memory Accesses, US Patent number 6,799,257 (September 28, 2004).
Assignee: Intel Corporation.
Invited Talks and Lectures
1. Memory Systems in the Multi-Core Era (An Accelerated Course) or Scalable Memory Systems in the Multi-Core Era
Beihang University, 3-day Lecture Series (16 hours), Beijing, China, June 17, 25, 26, 2012.
Seoul National University, 2-day Lecture Series (6 hours), Seoul, Korea, June 18, 20, 2012. (Memory Scaling and Memory QoS)
2. Some Ideas in Designing Scalable and Ef cient Multi-Core Systems
Apple, Cupertino, CA, 6 June 2012.
3. Concurrent Autonomous Self-Test for Uncore Components in SoCs
SK Hynix, Seoul, Korea, 23 June 2012.
4. Scaling the Main Memory System in the Many-Core Era or Main Memory Scaling: Some Ideas to Improve DRAM and Enable Hybrid
Memory Systems or Main Memory Scaling: Some Challenges and Solution Directions
IBM, Poughkeepsie, NY, 21 May 2012.
Invited Talk, ACM Design Automation Conference More Than Moore Technologies Workshop, San Francisco, CA, 3 June 2012.
Samsung Information Systems America, San Jose, CA, 4 June 2012.
Rambus, Sunnyvale, CA, 5 June 2012.
POSTECH, Pohang, Korea, 19 June 2012.
Samsung, Memory Division, Hwasung City, Korea, 21 June 2012.
SK Hynix, Seoul, Korea, 23 June 2012.
Distinguished Lecture at Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 28 June 2012.
Intel, Hillsboro, OR, 26 July 2012.
Advanced Micro Devices, Austin, TX, 21 September 2012.
McGill University, Montreal, Quebec, Canada, 1 October 2012.
5. Architecting and Exploiting Asymmetry in Multi-Core Architectures
Intel, Santa Clara, CA, 9 March 2011.
Rambus, Sunnyvale, CA, 5 June 2012.
Samsung, System LSI Division, Hwasung City, Korea, 22 June 2012.
Intel, Hillsboro, OR, 26 July 2012.
Advanced Micro Devices, Bellevue, WA, 3 August 2012.
Intel Archfest, Hillsboro, OR, 10 August 2012.
Intel Science and Technology Center on Cloud Computing Board of Advisors Meeting, 16 August 2012.
Intel Science and Technology Center on Cloud Computing Retreat, 29 November 2012.
6. Designing QoS-Aware Memory Systems or Predictable Memory Systems for the Many-Core Era
IBM, Poughkeepsie, NY, 21 May 2012.
SK Hynix, Seoul, Korea, 23 June 2012.
Intel, Hillsboro, OR, 1 August 2012.
VMware, Palo Alto, CA, 17 October 2012.
7. Main Memory Issues (Both Volatile and Non-Volatile)
Carnegie Mellon University Parallel Data Lab Retreat, Bedford, PA, 6 November 2012.
Carnegie Mellon University Parallel Data Lab Visit Day, Pittsburgh, PA, 11 May 2012.
8. Some (Security-Related) Challenges in Future Computing Platforms
Carnegie Mellon University College of Engineering Deans Council Meeting, Pittsburgh, PA, 26 April 2012.
9. Some Opportunities and Obstacles in Cross-Layer and Cross-Component (Power) Management
NSF Workshop on Cross-Layer Power Optimization and Management, Los Angeles, CA, 10 February 2012.
10. Memory Systems in the Many-Core Era: Challenges, Opportunities, and Solution Directions
Joint Keynote Talk, International Symposium on Memory Management (ISMM) and ACM Workshop on Memory System Perfor-
mance and Correctness (MSPC), San Jose, CA, 5 June 2011.
Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, 10 August 2011.
Tsinghua University, Beijing, China, 11 August 2011.
Microsoft Research Asia, Beijing, China, 15 August 2011.
Massachusetts Institute of Technology, 4 November 2011.
University of California at Berkeley (PARLAB seminar), 15 November 2011.
11. Issues in DRAM and NVM based Main Memory
Carnegie Mellon University Parallel Data Lab Retreat, Bedford Springs, PA, 8 November 2011.
12. Computer Performance
Carnegie Mellon University ECE Department Advisory Board Presentation, 21 September 2011.
13. Application-Aware Memory Controllers or Thread Cluster Memory Scheduling
Xilinx Labs, San Jose, CA, 8 June 2011.
Gigascale Systems Research Center Mid-Year Review, Yorktown Heights, NY, 27 May 2011.
14. Architecture and System-Level Challenges Related to Memory
Focus Center Research Program Memory Cross-Cut Workshop, Cambridge, MA, 12 May 2011.
15. Towards Practical Bufferless On-Chip Networks
Intel, Santa Clara, CA, 9 March 2011.
16. Some Ideas for Ef cient and High-Performance Core Design
Intel Corporation ARO Swiss Army Processor Workshop, Hillsboro, OR, 29 April 2011.
17. PCM (NVM) as Main Memory: Opportunities and Challenges
Carnegie Mellon University, Parallel Data Lab Retreat, Pittsburgh, PA, October 25, 2010.
18. Research Challenges in Future Computing Platforms
Carnegie Mellon University, ECE Department Faculty Retreat, Wheeling, WV, August 12, 2010.
19. Multi-core Architectures and Shared Resource Management: Fundamentals and Recent Research
Seoul National University, Lecture Series (12 hours), Seoul, Korea, July 6-9, 2010.
Korea Advanced Institute of Science and Technology, Global Lecture Series (15 hours), Daejeon, Korea, July 26-29, 2010.
Beihang University, 2-day Lecture Series (13 hours), Beijing, China, August 9, 12, 2011.
20. End-to-end QoS-aware, High-Performance and Customizable Many-Core Memory Systems
Intel Memory Hierarchy Meeting, Hillsboro, OR, 8 October 2010.
21. Rethinking Core Design in the Power-Constrained Many-Core Era
Intel Core Workshop, Hillsboro, OR, 27 September 2010.
22. Some Ideas for ILP Research
CRA Workshop on Advancing Computer Architecture Research, Seattle, WA, 20 September 2010.
23. Designing High-Performance and Fair Shared Multi-core Memory Systems: Two Approaches or QoS-Aware Multi-Core Memory
System Management
Gigascale Systems Research Center E-Seminar, 23 March 2010.
Pennsylvania State University, CSE Colloquium, 26 March 2010.
ARM, Inc., Austin, TX, 8 April 2010.
Advanced Micro Devices, Austin, TX, 9 April 2010.
Microsoft Research, Redmond, WA, 27 April 2010.
HP Laboratories, Palo Alto, CA, 25 May 2010.
VMware, Palo Alto, CA, 26 May 2010.
Intel Corporation, Hillsboro, OR, 27 May 2010.
Gigascale Systems Research Center Annual Review, San Jose, CA, 29 September 2010.
Intel Corporation ArchFest, Hillsboro, OR, 8 October 2010.
ASPLOS 2011 Program Committee Symposium, Pittsburgh, PA, 22 October 2010.
Advanced Micro Devices, Sunnyvale, CA, 10 March 2011.
Oracle, Redwood Shores, CA, 11 March 2011.
Princeton University, Princeton, NJ, 18 March 2011.
24. Rethinking Memory System Design in the Nanoscale Many-Core Era
Intel Memory Hierarchy Workshop, Hillsboro, OR, 22 January 2010.
ASPLOS Workshop on Architecting Memory Technologies, Pittsburgh, PA, 14 March 2010.
25. Asymmetry Everywhere (with Automatic Resource Management)
CRA Workshop on Advancing Computer Architecture Research, San Diego, CA, 22 February 2010.
26. Preventing Memory Performance Attacks in Multi-Core Systems
ECE Seminar, Carnegie Mellon University, 5 February 2009.
Massachusetts Institute of Technology, 23 April 2008.
Carnegie Mellon University, 15 April 2008.
27. Parallelism-aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
IBM Austin Research Laboratory, Austin, TX, 19 June 2009.
Advanced Micro Devices Research Lab, Redmond, WA, 6 March 2009.
Beihang University, Beijing, China, 21 June 2008.
28. ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers
Advanced Micro Devices Research Lab, Redmond, WA, October 2009.
Freescale Semiconductor, Austin, TX, 8 April 2010.
29. Memory Performance Attacks and Fair Memory Scheduling
University of British Columbia and IEEE Computer Society, Vancouver, BC, Canada, 6 March 2008.
ASPLOS PC Meeting Research Seminar, Microsoft Research, 18 October 2007.
Multi-Core Virtual Team Meeting, Microsoft, 5 October 2007.
30. MSR Computer Architecture Group: Vision and Projects
Presentation to Rico Malvar, MSR-Redmond Director, Microsoft Research, 12 December 2007.
31. Hardware-Based Devirtualization of Virtual Function Calls
MSR Systems and Networking Seminar, Microsoft Research, 7 December 2006.
32. Runahead Execution and AVD Prediction: A Power-ef cient Processing Paradigm for Tolerating Long Main Memory Latencies
University of Illinois Urbana-Champaign, Computer Engineering Seminar, Urbana, IL, USA, 23 January 2007.
Xilinx Labs, San Jose, CA, USA, 16 June 2006.
Microsoft Research, Redmond, WA, USA, 12 June 2006.
Stanford University, Department of EE, Computer Architecture Seminar, Stanford, CA, USA, 7 June 2006.
MIPS Technologies, Mountain View, CA, USA, 6 June 2006.
IBM T.J. Watson Research Center, Yorktown Heights, NY, USA, 1 June 2006.
Carnegie Mellon University, Department of ECE, CALCM Seminar, Pittsburgh, PA, USA, 30 May 2006.
Hewlett-Packard Laboratories, Palo Alto, CA, USA, 4 May 2006.
University of California, San Diego, Department of Computer Science and Engineering, CA, USA, 21 April 2006.
University of Texas at Austin, Department of ECE, Guest Lecture for EE382N (Microarchitecture), 11-12 April 2006.
33. Ef cient Runahead Execution
Advanced Micro Devices, Sunnyvale, CA, USA, May 2005.
Intel Barcelona Research Center, Barcelona, Spain, November 2005.
34. Runahead Execution
Advanced Micro Devices, Sunnyvale, CA, USA, May 2004.
Instituto de Informatica, Universidade Federal Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, October 2004.
35. Runahead Execution: A Mechanism to Approximate the Performance of Large Instruction Windows
Enterprise Platforms Group, Intel Corporation, Santa Clara, CA, USA, August 2002.
Desktop Platforms Group, Intel Corporation, Hillsboro, OR, USA, August 2002.
Conference Talks
36. Flash Correct-and-Refresh: Retention-Aware Error Management for Increased Flash Memory Lifetime, 30th International Conference
on Computer Design, Montreal, Quebec, Canada, September 2012.
37. Bottleneck Identi cation and Schedulingin Multithreaded Applications, 17th International Conference on Architectural Support for Pro-
gramming Languages and Operating Systems, London, UK, March 2012.
38. Data Marshaling for Multi-core Architectures, 37th International Symposium on Computer Architecture, St. Malo, France, June 2010.
39. Parallelism-aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, 35th International Sympo-
sium on Computer Architecture, Beijing, China, June 2008.
40. Stall-Time Fair Memory Access Scheduling, 40th International Symposium on Microarchitecture, Chicago, IL, USA, December 2007.
41. Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems, 16th USENIX Security Symposium, Boston, MA,
USA, August 2007.
42. Address-Value Delta Prediction, 38th International Symposium on Microarchitecture, Barcelona, Spain, November 2005.
43. Techniques for Ef cient Processing in Runahead Execution Engines, 32nd International Symposium on Computer Architecture, Madison,
WI, USA, June 2005.
44. Wrong Path Events and Their Application to Early Misprediction Detection and Recovery, 37th International Symposium on Microar-
chitecture, Portland, OR, USA, December 2004.
45. Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance, 16th
Symposium on Computer Architecture and High Performance Computing, Foz do Iguacu, Brazil, October 2004.
46. Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, 9th International Conference on
High Performance Computer Architecture, Anaheim, CA, USA, February 2003.
Teaching Experience
Carnegie Mellon University, ECE Department, Instructor for Undergraduate Computer Architecture Course ECE-447, Spring 2012
Instructor rating based on student evaluations: 4.12/5.0 (Fall 10, 34/47 students responded)
Carnegie Mellon University, ECE Department, Instructor for Graduate Computer Architecture Course CS/ECE-740, Fall 2010, 2011
Instructor rating based on student evaluations: 4.42/5.0 (Fall 10, 43/53 students responded), 4.7/5.0 (Fall 11, 19/24 responded)
Carnegie Mellon University, ECE Department, Instructor for Parallel Computer Architecture Course ECE-742, Spring 2010, 2011, Fall 2012
Instructor rating 4.44/5.0 (Spring 10, 18/20 students responded), 4.71/5.0 (Spring 11, 7/10 responded)
Carnegie Mellon University, ECE Department, Instructor for Advanced Computer Architecture Course ECE-741, Spring 2009
Instructor rating based on student evaluations: 4.6/5.0 (25/35 students responded)
University of Texas at Austin, ECE Department, Teaching Assistant for Senior-level Computer Architecture Course EE360N, Spring 2003
Instructor rating based on student evaluations: 4.7/5.0 (59/70 students responded)
University of Texas at Austin, ECE Department, Teaching Assistant for Senior-level Computer Architecture Course EE360N, Spring 2001
Instructor rating based on student evaluations: 4.8/5.0 (30/50 students responded)
University of Texas at Austin, ECE Department, Teaching Assistant for Freshman-level Intro. to Computing Course EE306, Fall 2000
Instructor rating based on student evaluations: 4.7/5.0 (35/55 students responded)
Supervised Students
Current PhD Students at CMU: Rachata Ausavarungnirun, Kevin Chang, Chris Fallin, Benjamin Jaiyen, Yoongu Kim, Donghyuk Lee, Jamie
Liu, Justin Meza, Gennady Pekhimenko, Vivek Seshadri, Lavanya Subramanian, Hongyi Xin, Han Bin Yoon
Undergraduate Research Students at CMU: Yuchen Hao (Tsinghua), Rachael Harding (grad. Dec 2010), Gregory Nazario, Harsha Rastogi
(BITS Pilani), Kevin Woo, Samihan Yedkar, Xiangyao Yu (Tsinghua)
Masters Research Students at CMU: Chris Craik (grad. Aug 2011), Mughda Satish Dharkar, Huimin Yang
Current Mentees at UT-Austin: Milad Hashemi, Jose Joao, Khubaib, Rustam Miftakhutdinov, Veynu Narasiman
Internship Manager of: Rishi Agarwal (IIT-Kanpur), Kypros Constantinides (Michigan), Alejandro Cornejo (MIT), Reetuparna Das (Penn
State), Eiman Ebrahimi (UT-Austin), Boris Grot (UT-Austin), Engin Ipek (Cornell), Jose Joao (UT-Austin), Yanjing Li (Stanford), Gregory
Nazario (CMU), Xuehai Qian (Illinois), Xiangyao Yu (Tsinghua)
Ph.D. Thesis Committee Member of: Akkarit Sangpetch (CMU), Asit Mishra (Penn State), Chen-Ling Chou (CMU), Reetuparna Das (Penn
State), Eiman Ebrahimi (UT-Austin), Michael Ferdman (CMU), Boris Grot (UT-Austin), Engin Ipek (Cornell), Lei Jin (Pitt), Karthik Lakshmanan
(CMU), Chang Joo Lee (UT-Austin), Olatunji Ruwase (CMU), Marek Telgarsky (CMU), Yu Cai (CMU)
Professional Service
Technical Journal Editorships
Associate Editor, ACM Transactions on Architecture and Code Optimization, Feb. 2010 - Present.
Co-Guest Editor, IEEE Micro special issue (May/June 2008) on The Interaction of Computer Architecture and Operating Systems in the Many-
core Era, May/June 2008.
Co-Guest Editor, IEEE Micro special issue (Jan/Feb 2011) on Micro s Top Picks from Computer Architecture Conferences, Jan/Feb 2011.
Technical Conference Program and Steering Committee Chairmanships
MICRO Program Chair, 45th ACM/IEEE International Symposium on Microarchitecture, 2012.
MSPC Program Chair, ACM SIGPLAN Workshop on Memory System Performance and Correctness, 2012.
IEEE Micro Top Picks Selection Committee Co-Chair, IEEE Micro Special Issue on Top Picks from Computer Architecture Conferences, 2011.
IISWC Program Co-Chair, 4th IEEE International Symposium on Workload Characterization (IISWC), 2008.
Technical Conference Program and Steering Committee Memberships
IEEE Micro Top Picks Selection Committee Member, IEEE Micro Special Issue on Top Picks from Computer Architecture Conferences, 2013,
2012, 2011, 2010, 2009.
ISCA Program Committee Member, International Symposium on Computer Architecture, 2010, 2008.
MICRO Program Committee Member, International Symposium on Microarchitecture, 2012, 2008, 2007 (Did not accept invitation in 2011, 2010
due to paper submission limits).
ASPLOS Program Committee Member, Intl. Conf. on Architectural Support for Programming Lang. and Operating Systems, 2012, 2011, 2009.
HPCA Program Committee Member, International Symposium on High Performance Computer Architecture, 2012, 2010, 2009.
PACT Program Committee Member, International Conference on Parallel Architectures and Compilation Tecniques, 2013.
ISMM Program Committee Member, International Symposium on Memory Management, 2013.
ICAC Program Committee Member, International Conference on Autonomic Computing, 2013.
ICCD Program Committee Member, IEEE International Conference on Computer Design, 2012, 2011, 2010, 2009.
IIS
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