Design Management
Resume:
KRISHNA SEKAR
****A Regents Road, Phone: 858-***-****
La Jolla, CA 92037 Email: abqac2@r.postjobfree.com
http://esdat.ucsd.edu/~ksekar
OBJECTIVE
Full-time position that utilizes my extensive knowledge and experience in
the areas of embedded systems, platform-based design, system-on-chips (SoCs),
VLSI design and CAD/EDA for digital circuits
EDUCATION
Ph.D. in Electrical and Computer Engineering 2001 - July 2005 (expected)
University of California, San Diego GPA: 3.9
Advisor: Prof. Sujit Dey
Dissertation Title: "Dynamic Platform Management for Configurable
Platform-Based System-on-Chips"
M.S. in Electrical and Computer Engineering 1999 - 2001
University of California, San Diego
B.Tech (with Honors) in Computer Science and Engineering 1995 - 1999
Indian Institute of Technology, Kharagpur
RELEVANT SKILLS
* Strong R&D background in embedded systems, platform-based SoCs, VLSI
design & testing, and CAD/EDA for digital circuits, with several
research publications in leading journals and conferences
* Demonstrated performance and power benefits of dissertation research
on a real platform (Altera Excalibur), including development of
complete software infrastructure (bootcode, OS, applications)
* Software programming skills: C, C++, Java, Perl, Matlab, Assembly
* Hardware design skills: Verilog, VHDL, SystemC, full custom design
* Experience in numerous CAD/EDA tools: HW synthesis (Design Compiler,
Leonardo), Simulation (ModelSim, VCS, IRSIM, Spice), HW/SW design and
co-verification (Seamless CVE, Cadence VCC, Cocentric System Studio,
ARMulator), ATPG and testing (DFTA, LBISTA, MBISTA, FastScan, Flextest)
* Grad Courses: Computer Architecture, VLSI Architectures & Algorithms,
CAD for VLSI, VLSI Design & Testing, Computer Networks, Operating
Systems, Compiler Design, Design & Analysis of Algorithms
WORK EXPERIENCE
Mobile Embedded Systems Design & Test Group, Aug. 1999 - present
Dept. of ECE, UC San Diego
Graduate Research Assistant
* Conducted dissertation research on dynamic management and configuration
of multiple SoC platform components (CPU, memory, bus, cache) for
high-performance and low-power mobile systems
System LSI Group, NEC Laboratories, Princeton, NJ June - Sept. 2004
Research Intern
* Developed novel re-configurable on-chip communication architectures for
high-performance SoCs
SoC Verification Division, June - Sept. 2001
Mentor Graphics Corp., Wilsonville, OR
Summer Intern
* Developed C based, cycle-accurate simulation models of SoC peripherals
for HW-SW co-simulation
Fujitsu Laboratories of America, Sunnyvale, CA June - Sept. 2000
Research Intern
* Developed design-for-verification techniques at the register transfer
level to improve design verifiability
Dept. of ECE, UC San Diego
Teaching Assistant
* Designed and conducted laboratory projects on embedded systems, and
testing of digital circuits
* Advanced Digital Design Project Spring 2002, Winter 2003
(Embedded Systems Design)
* Advanced Topics in VLSI Spring 2000, Spring 2003
(System-on-Chip Design and Test)
Synopsys India R&D Office, Bangalore, India May - July 1998
Summer Intern
* Worked on benchmark testing and porting of Verilog Compiled Simulator
(VCS) to Windows NT
PUBLICATIONS
Journal Articles
* Dynamic platform management for configurable platform-based
system-on-chips,
K.Sekar, K.Lahiri and S.Dey,
submitted to IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems.
* LI-BIST: A low-cost self-test scheme for SoC logic cores and
interconnects,
K.Sekar and S.Dey,
Journal of Electronic Testing: Theory and Applications, vol.19, no.2,
pp.113-123, April 2003.
* Using a soft core in a SoC design: experiences with picoJava,
S.Dey, P.Sanchez, D.Panigrahi, L.Chen, C.Taylor, and K.Sekar,
IEEE Design and Test of Computers, vol.17, no.3, pp.60-71,
July-September 2000.
Conference Papers
* FLEXBUS: A high-performance system-on-chip communication architecture
with a dynamically configurable topology,
K.Sekar, K.Lahiri, A.Raghunathan and S.Dey,
to appear in Proc. Design Automation Conference,
Anaheim, June 2005.
* Configurable platforms with dynamic platform management: an efficient
alternative to application-specific system-on-chips,
K.Sekar, K.Lahiri and S.Dey,
in Proc. Intl. Conf. on VLSI Design, pp.307-315, Mumbai, January 2004.
* Dynamic platform management for configurable platform-based
system-on-chips,
K.Sekar, K.Lahiri and S.Dey,
in Proc. Intl. Conf. on Computer-Aided Design, pp. 641-648, San Jose,
November 2003.
* LI-BIST: A low-cost self-test scheme for SoC logic cores and
interconnects,
K.Sekar and S.Dey,
in Proc. VLSI Test Symposium, pp.417-422, Monterey, May 2002.
* Design for verification at the register transfer level,
I.Ghosh, K.Sekar and V.Boppana,
in Proc. Intl. Conf. on VLSI Design/Asia South Pacific Design
Automation Conference (ASP-DAC), pp.420-425, Bangalore, January 2002.
* Abstraction of word-level linear arithmetic functions from bit-level
component descriptions,
P.Dasgupta, P.P.Chakrabarti, A.Nandi, K.Sekar and A.Chakrabarti,
in Proc. Design, Automation and Test in Europe, pp.4-8, Munich,
March 2001.
* Embedded hardware and software self-testing methodologies for
processor cores,
L.Chen, S.Dey, P.Sanchez, K.Sekar and Y.H.Chen,
in Proc. Design Automation Conference, pp.625-630, Los Angeles,
June 2000.
AWARDS
* IEEE VLSI Test Symp. Special Service Award for outstanding contributions
to its organization, 2003
* Jagadish Bose National Science Talent Search Award for excellence in
science, India, 1995
* TISCO scholarship for entire duration of undergraduate studies, India,
1995
ACTIVITIES
* Reviewer for leading journals and conferences: IEEE Trans. on VLSI
Systems, IEEE Trans. on CAD for Integrated Circuits and Systems, ACM
Trans. on Embedded Computing Systems, IEEE/ACM Design Automation
Conference, Intl. Symp. on HW/SW Co-design, Intl. Test Conf., Intl.
Conf. on VLSI Design
* Web administrator of IEEE VLSI Test Symposium, 2003
* Student member of IEEE and the IEEE Circuits and Systems Society
(since 1999)
Contact this candidate