Power Design

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. **, NO. 1, JANUARY 2003 141

Single-Ended to Differential Converter for Multiple-Stage

Single-Ended Ring Oscillators

Yuping Toh, Member, IEEE, and John A. McNeill, Member, IEEE

Abstract This paper presents an improved technique for

single-ended to differential conversion that allows for the use of

single-ended CMOS ring oscillators in an otherwise fully differ-

ential integrated circuit environment. An interpolating resistor

network is used to derive a fully differential representation of

the single-ended voltage-controlled-oscillator (VCO) signal. The

technique preserves the fundamental noise performance of single-

ended ring oscillators in the presence of supply and substrate

interference. Experimental results in a 0.35- m CMOS process

show the applicability of this technique at the VCO speeds of up

to 1.3 GHz.

Index Terms Jitter, phase noise, power-supply interference,

power-supply noise, single-ended to differential conversion, sub-

strate noise, voltage-controlled oscillator.

(a)

I. INTRODUCTION

A CHALLENGE in the design of integrated oscillators is

the preservation of fundamental phase noise performance

in the presence of supply and substrate interference. Although

better fundamental phase noise performance is achieved with

LC-based oscillators, CMOS ring oscillators are easier to inte-

grate [1] and consume less die area. In either case, differential

circuits and signals are often employed because of their good

rejection of common-mode supply and substrate noise and

their lower noise injection into other circuits. On the other

hand, single-ended CMOS ring oscillators have better thermal

noise performance than their differential CMOS counterparts

and can achieve better phase-noise performance for a given

power dissipation [2], [3]. The lower thermal noise jitter in

single-ended ring oscillators (SROs) is largely due to the

larger voltage swings than those available in differential ring

oscillators (DROs). DRO voltage swings are typically limited

to approximately a threshold voltage because of headroom

constraints. Furthermore, it has been shown that saturated-type

oscillators, which fully switch the devices in the delay cell, (b)

exhibit better phase-noise performance than nonsaturated-type

Fig. 1. (a) Single-ended to differential conversion circuit using a single phase

oscillators [1]. SROs fall under the category of saturated-type and dc average of the ring. (b) Waveforms for Fig. 1(a).

oscillators.

While their lower thermal noise jitter is attractive, SROs are

used in an otherwise fully differential integrated circuit environ-

susceptible to supply noise due to their single-ended signal path.

ment. As will be shown in Section II, it is difficult to develop a

Reducing this susceptibility with techniques such as capacitive

high-quality differential version of the single-ended ring signal.

bypassing and supply regulation [4], [5] provides a low-noise,

In Section III, an improved method of performing the single-

single-ended clock signal with acceptable immunity to supply

ended to differential conversion in a three-stage ring oscillator

and substrate noise. However, it may be the case that the SRO is

is described. Sections IV and V describe design considerations

and experimental results; Section VI describes possible gener-

Manuscript received August 2, 2001; revised June 28, 2002. This work was

alization to ring oscillators with more than three stages.

supported by National Science Foundation under Award 9701408.

Y. Toh was with the Worcester Polytechnic Institute, Worcester, MA 01609

USA. He is now with Analog Devices, Wilmington, MA 01887 USA (e-mail:

II. SINGLE-ENDED TO DIFFERENTIAL CONVERSION

******.***@******.***).

J. A. McNeill is with the Worcester Polytechnic Institute, Worcester, MA

Figs. 1(a) and 2(a) show two possible methods of performing

01609 USA.

single-ended to differential conversion of the output of a CMOS

Digital Object Identifier 10.1109/JSSC.2002.806262

0018-9200/03$17.00 2003 IEEE

142 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003

(a)

(a)

(b)

(b) Fig. 3. (a) Improved single-ended to differential conversion circuit using

interpolating resistor network. (b) Waveforms for Fig. 3(a).

Fig. 2. (a) Single-ended to differential conversion circuit using two phases of

the ring. (b) Waveforms for Fig. 2(a).

from the ideal differential representation of the single-ended

SRO. In each case, a PMOS differential pair, formed by tran-

ring signal. The two major nonidealities are duty-cycle distor-

sistors and, is used as a simple comparator and level

tion and waveform asymmetry. The main cause of these non-

shifter to develop the desired output signals and,

idealities is the varying common mode of the inputs and

which are the differential representation of the single-ended ring, shown as the dashed waveform in Figs. 1(b) and

signal. The differential pair is biased by current, which is de-

2(b). Although low-frequency common-mode variations are re-

veloped by current source with bias voltage . Capacitor

jected by the differential pair, at higher frequencies, common

represents the sum of all parasitic capacitances at node .

mode rejection is reduced significantly due to . Variation in

In the approach shown in Fig. 1(a), the comparator input

causes variation in the voltage, which in turn causes a

is obtained from one phase of the ring and input from a

variation in differential pair bias current in accordance with

half-amplitude reference developed by shorting the output

. This variation in results in amplitude variations

and input of a replica ring stage.

at the differential pair output.

In the approach shown in Fig. 2(a), the comparator inputs are

obtained from two phases of the ring [6]. This approach elimi-

nates the need to develop the half-amplitude reference required III. IMPROVED CONVERSION TECHNIQUE

in the approach of Fig. 1(a).

A. Development of Improved Technique

Figs. 1(b) and 2(b) show the waveforms associated with each

approach. Idealized waveforms are shown for comparator in- Fig. 3(a) shows the single-ended to differential conversion

puts and ; also shown are simulated output waveforms technique developed in this work. In this approach, the same

in a 0.35 m CMOS process. It can be seen from the simulated differential pair is used but the inputs and are taken

waveforms that outputs and deviate significantly from an interpolating network. Assuming resistors R1 through

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003 143

R4 to be of equal value, the outputs of the interpolating network

are given by

(1)

(2)

Fig. 4. Noise model.

The function of the interpolating network is to develop a

differential representation of the SRO signal with a constant

common mode component. To see how this function results, we IV. DESIGN CONSIDERATIONS

first develop idealized expressions for the phase voltages,

A. Resistor Value, and .

In this work, the interpolating resistors through were

At each stage of the ring, the oscillator waveform propagates

implemented using N-well resistors with a nominal value of

with a phase lag of radians (due to the stage delay) as well

20 k . This value results from an optimization between con-

as an inversion ( radians). Although the ring oscillator is

flicting design drivers. A high resistance is desired so as to min-

often thought to be a square wave oscillator, at high speeds

imize current drawn from the VCO. The value of through

the waveforms in a three-stage ring are more nearly sinusoidal.

cannot be increased arbitrarily for a number of reasons. A high

If we idealize the waveforms to be sinusoidal with equal delay

value will reduce the maximum operating frequency of the cir-

in each stage, then, the voltage waveforms at each phase can be

cuit due to the RC lowpass formed between the resistor and the

represented as

input gate capacitance of the differential pair transistors. Addi-

tionally, high-resistor values will increase thermal noise.

(3)

B. Noise

(4)

Fig. 4 shows a circuit model that can be used to determine the

effect of noise from one of the interpolation resistors. Analysis

(5) of the effect on phase noise requires use of the impulse-sensi-

tivity-function technique [7] due to the time-varying impedance

at the delay stage output. Simulation shows that for the re-

with sinusoid frequency, peak amplitude and dc average

sistor values used in this work, the additional noise contribution

. Substituting (3) (5) into (1) and (2) and performing some

does not significantly degrade VCO phase noise performance.

trigonometric manipulation, gives

In general, it may be the case that other design constraints

dictate resistor values that would degrade VCO phase noise per-

formance. In that case, the gate outputs could be buffered prior

(6)

to interpolation. Although buffers would add jitter in the signal

path to the eventual differential output, the jitter would be out-

(7)

side the VCO ring and would not accumulate.

Note that noise of the PMOS differential pair (and of any

Thus, (6) and (7) show that and constitute a subsequent sources referred to the PMOS differential pair input)

signal pair with common mode and differential signal is outside the VCO ring and does not accumulate. Therefore,

. VCO jitter performance is dominated by the jitter accumulated

Fig. 3(b) shows the waveforms associated with the approach within the VCO ring.

of Fig. 3(a). The idealized waveforms for comparator inputs

C. Resistor Matching

and show a constant common mode component

. It can be seen that the simulated outputs The differential nature of the signal pair was

and exhibit much improved duty cycle regularity and derived assuming equal values of resistors in the and

amplitude symmetry. interpolating networks. The interpolation technique

In practice, is not constant since the signal from each depends on resistor ratios and is therefore tolerant of process

phase of the voltage-controlled oscillator (VCO) is not purely si- and temperature variations in absolute resistor values; however,

nusoidal; for a three-stage VCO operating near maximum speed the effects of mismatch must be considered. The analysis [8] is

the assumption of pure sinusoids is only approximately true. simplified by considering separately the effects of mismatch in

This results in some variation in, which causes small varia- the and interpolating networks.

tions in and . This in turn causes the slight variation in the It can be shown that mismatch (in the network

amplitudes of and as shown in the simulated wave- interpolating between phases and ) leads to a phase

forms in Fig. 3(b). Even with these slight variations, waveform error in . Defining mismatch variables for and

symmetry shows significant improvement over the cases shown

in Figs. 1(b) and 2(b) (8)

144 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003

Fig. 5. Chip micrograph.

(9)

Fig. 6. 640-MHz VCO output waveform after division by 8.

analysis [8] shows that the phase error (in radians) for

is related to the fractional mismatch by

(10)

In analogous fashion, mismatch (in the network

interpolating between ring phase and the dc average signal

) leads to an amplitude error in . With mismatch variables

(11)

(12)

analysis shows that the amplitude error for is related

to the fractional mismatch by

(a)

(13)

or for the fractional amplitude error :

(14)

The results in (10) and (14) indicate that the matching require-

ments are modest: a fractional mismatch of 2% corresponds to

a phase error of 1 or an amplitude error of 1%.

V. EXPERIMENTAL RESULTS

The VCO output buffer in this work was implemented in sil-

icon using the TSMC 4-metal 1-poly 0.35 m CMOS process.

A chip micrograph is shown in Fig. 5. The total area consumed

(b)

by the VCO, interpolating resistors and differential pair level

Fig. 7. (a) Simulated output, simple differential pair buffer [Fig. 1(a)]. Jitter

shifter is m m. At maximum speed, power con-

= 9.85-ps rms Horizontal: 5 ps/div. Vertical: 20 mV/div. (b) Simulated output,

improved differential pair buffer [Fig. 3(a)]. Jitter = 1.73-ps rms Horizontal:

sumption of the ring VCO core is 80 mW. Additional power

consumption of the single-ended to differential conversion cir- 5 ps/div. Vertical: 20 mV/div.

cuitry is 5.3 mW. The circuit has been operated at VCO speeds

of up to 1.3 GHz. Fig. 6 shows the output waveform for a VCO

represents a 5 reduction from the 9.85-ps rms for the circuit

frequency of 640 MHz after an on-chip divide-by-8.

of Fig. 1(a).

To examine performance in the presence of power supply

noise, the circuit configurations of Figs. 1(a) and 3(a) were sim-

VI. GENERALIZATION OF TECHNIQUE

ulated with a 200-mV pk-pk, 100-MHz sine wave superimposed

on the 3.3-V power supply. Zero-crossing times of the output It is logical to consider whether this technique can be gener-

differential waveforms are shown in Figs. 7(a) and (b). Jitter for alized to rings with more than three stages. One possible gen-

the circuit using the improved technique is 1.73 ps rms, which eralization, to expand the interpolating networks and connect

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003 145

cability of the technique, however; the need for this technique

arose from the problems associated with the high frequency sig-

nals present in the three-stage ring oscillator.

(a) VII. CONCLUSION

An improved technique for single-ended to differential con-

version has been presented that allows for the use of single-

ended CMOS ring oscillators in an otherwise fully differen-

tial integrated circuit environment. The technique preserves the

fundamental noise performance of single-ended ring oscillators

in the presence of supply and substrate interference. This tech-

nique uses an interpolating network of resistors to derive a fully

differential representation of the single-ended VCO signal. Ex-

(b) perimental results in a 0.35- m CMOS process show the appli-

cability of this technique at VCO speeds of up to 1.3 GHz.

Fig. 8. (a) Interpolation example for seven-stage ring. (b) Phasor representa-

tion for seven-stage ring.

ACKNOWLEDGMENT

alternate stages to alternate sides, is shown for the example of a The authors thank C. Liu for assistance with jitter simula-

seven-stage ring in Fig. 8(a). The most straightforward general- tions. The authors also thank the reviewers for their careful con-

ization assumes sinusoidal waveforms; this assumption is indi- sideration and helpful comments.

cated with the sinusoid inside the gate symbol in Fig. 8(a).

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