Looking for a Digital VLSI Design/Advanced Hardware Design Engineering

Mohamed Anis Weldon

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street, Ozone Park, NY-11417, USA Tel: 347-***-**** Email: ********@********.****.***/**********@*****.***/**********@*****.***

Education Polytechnic Institute of New York University, Brooklyn, USA May 2013 (Expected) Masters of Science, Computer Engineering GPA: 3.71

M.H. Saboo Siddik College of Engineering, Mumbai, India May 2011 Bachelors of Engineering, Electronics Engineering GPA: 3.30

Skills Expertise: Digital CMOS and VLSI Design (transistor & Gate Level), Advanced Hardware Design, ASIC, SOC,

RTL, FPGA and Mixed Signal Designing

Languages and Software: C++, Perl, Python, Tcl Scripting, Assembly Language, VHDL/ Verilog(XILINX/MODELSIM),

Cadence (Allegro PCB Editor, Schematic Capture, Virtuoso Environment, RTL Compiler,

SOC Encounter), MATLAB, PSPICE

Operating Systems: Vista, Windows98/2000/NT/XP/7, LINUX Research and Publication Polytechnic Institute of New York University

Publication: STT-RAM Designs Supporting Dual-port Accesses Summer 2012

Design for Automation and Test in Europe (DATE 2013) Accepted

Research:

• Research of Dual Port Mechanism for Spin Torque Transfer RAM cell at 65nm Technology Node

• Implemented and Optimized the Design targeting the Design Metrics

• Analysis of the Schematic and the Layout of a Single cell using Cadence Virtuoso XL Environment

Master Thesis: Brain Neuronal learning and adaptation using Spike Timing Dependence Plasticity Fall 2012-Present

Research:

• Providing a Conceptual Proof on how STDP algorithm and Polychronous Groups concept can work

together to form the basis of how the human brain learns and adepts

• Modeling the Algorithm in MATLAB and carrying out extensive experiments to support the thesis

• Developed Skills like Reading Research papers, Experimental Protocols, Statistical Analyses Work Experience Polytechnic Institute of New York University

Teaching Assistant for Advance Hardware Design(VHDL) at Computer Engineering Department Jan 2013-Present

• Conducting Lab Lectures/Presentations on VHDL

• Designing and Grading Assignments and Quiz

• Helping students solving/debugging doubts/troubleshooting VHDL assignments and projects

Research Graduate Assistant at Computer Engineering Department Jan 2012–Dec 2012

• Research and Implementation of Spin Transfer Torque RAM (SPRAM)

• Implemented CMOS Transistor Level Schematic and Layout(65nm) of SPRAM Using Cadence

Virtuoso XL Environment

• Performed Functional and Timing Simulation, Testing and Analyses(Power, Area and bandwidth)

Project Work Polytechnic Institute of New York University

1. Ultra Low Power and Small Wireless System for ECOG signals Fall 2012

• Implemented a Mixed Signal small(size of a Quarter) Wireless Circuit which can fit into the animal skull to

monitor the ECOG signals and transfer the signals via a Bluetooth channel to receiver end

• Implemented Schematic using Allegro Schematic Capture, Observed functionality on PSPICE and

Implemented Layout on Allegro PCB editor

• Additionally performed tasks such as Creating Footprints, Bill of Materials (BOM), PCB manufacturing

with Advanced Circuits, parts ordering, Assembly and testing/troubleshooting. 2. Malicious Processor Design – Introducing Hardware Trojans in 8051 microcontroller Spring 2012

• Injected Hardware Trojans in 8051 microcontroller affecting its functionality.

• Leaked the secret Key of RC5 encryption algorithm implemented on 8051

microcontroller via the help of Trojan injected.

• Demonstrated various other hardware Trojans and their payload on 8051 microcontroller IC 3. ASIC design of MIPS pipeline CPU architecture Spring 2012

• Modeled and Developed VHDL code of MIPS V pipeline CPU architecture including functional and

timing simulation and verification

• Used Cadence RTL Compiler Tool to generate the Gate-Level Netlist and performed timing closures,

optimization and synthesis using TCL file

• Used Cadence SOC Encounter to generate the layout of the sub components and then partitioned

the Sub components into the top module and performed timing closures, optimization and

synthesis. 4. An Implementation of Gyroscopes and Accelerometers to Maintain the Orientation Spring 2012

of Two Systems/ Platforms

• Implemented a pair of gyroscopes and accelerometers on two Independent platforms with the aim

to keep the platforms parallel to each other, if the parallel orientation is disturbed.

• Communication between the four sensors with the help of 8051 microcontroller IC C8051F020.

• Calculated and used the angular difference to make the 2 platforms parallel to each other. 5. 32-bit Brent Kung Adder Design Fall 2011

• Designed Schematic and Layout using Cadence Virtuoso Environment.

• Performed Performance Analyses Using Cadence Virtuoso Environment. 6. Implementing Secure Hash Algorithm 1 (SHA1) Fall 2011

• Implemented Secure Hash function on XILINX ISE

• Performed Functional and timing Simulation and implementation on Basys2 FPGA Board M.H. Saboo Siddik College of Engineering

1. Location Based Smart Transit Fall2010–Spring 2011

• Monitored, displayed and sounded alert of the Vehicle’s Location with the help of GPS

2. Short Range Radar System Fall 2009

• System Sensed position of the intruder or the obstacle with the IR sensor and display

Achievements and Awards

• Member of IEEE 2009-10

• Awarded Second Place in Robotics Drag Race-SAE India & Best Design of ROBOT April 2009

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