Project Engineering

PRIYANKA SHARAN

Email: ***************@*****.***

Ph. 512-***-****

CAREER SUMMMARY

* ***** ** ****** **** experience in Physical Design as a part of Physical

Verification and Integration team.

OBJECTIVE

To work in a creative and challenging environment where I can grow and

contribute meaningfully

SKILLS

. Chip level Floorplanning including pin placement, power busing,

placement of blocks and macros in Encounter

. Chip level Routing of complex SOCs in 45nm technology using Cadence-

Encounter

. Clock Tree Synthesis, Timing Closure, Signal Integrity/Noise fixing

of SOCs in 45nm technology using Cadence-Encounter

. Dynamic power analysis using PTPX

. Synthesis using RC

. Layout Editing through Cadence Virtuoso ICFB and ICOA(OA database),

Calibre workbench

. DRC & LVS using Calibre, also acquainted with SVRF coding

. Spice generation

. Technologies well acquainted with : 45SOI, 90SOI, 90GP

. Tcl scripting and vim editing

. Excellent communication skills

EDUCATION

Bachelor of Engineering, Electronics and Communication Engineering, May

2007

Birla Institute of Technology, Mesra, Ranchi, India

CGPA - 8.33/10

Relevant Coursework

Basic Electronics, Pulse and Digital Circuits, Semiconductors Devices,

Microelectronics Engineering, Digital Signal Processing, Logic Design,

Microprocessor and Interfacing, VLSI Design, Digital Signal Processing

Architecture

PROJECT EXPERIENCE

Texas Instruments, Bangalore, India (Jan'11 - Jan'12)

. Aegis, an 45nm project (Sep'11 - Jan'12)

Responsibilities: Synthesis of all blocks and integration at the top

level in RC

. SubArctic, 45nm project (Jan'11 - Jun'11)

Responsibilities: Dynamic power estimation for chip-top

Assist in chip-top level STA (PrimeTime)

Freescale Semiconductors, Noida, India (Jul'07- Jan'11)

. PSC9131, a 45nm flip chip project ( Sep'10 - Dec'10)

Responsibilities: Bump pad placement, signal/power assignment, Bump

routing to the chip-pad of IO cells

Top layer Power grid generation

. P1023, 45nm project ( Dec'09-Jul '10)

Responsibilities: Chip Level Floorplanning including pin placement,

power grid creation and placement of blocks and hard macros

Clock Tree synthesis, Place & Route at chip level, Chip top Timing

closure

Signal integrity and Noise fixing

Formal Equivalence checking and correction

Assist in the Physical Verification and chip-top level integration

including DRC, LVS, Antenna fixing, DFM, Mimcap generation, Tiling and

other chip finishing activities

. P1022 - 45nm project (Mar'08-Aug'09)

Responsibilities: Understanding of the 45SOI technology DRM, Chip top

level Physical Verification activities including DRC, LVS, Antenna

rules understanding and violation fixing, DFM, Mimcap addition,

Tiling, IO data generation for early power analysis and estimation,

custom designing of IO ring corner cells layout, custom layout

designing of crack ring and delay element and other chip finishing and

integration activities

. Beagle- a 90SOI project (Nov'07- Feb'08)

Responsibilities: DRC, LVS, Spice Generation, Tiling activities of

chip level database and fracture data verification

. 8311 rev1.2 and 8315 rev2.0 (90gp projects)-DRC and LVS correction of

module level databases

RESEARCH EXPERIENCE

. Designed "Antenna Immune Power grid in 45SOI Technology", which was

implemented in P1023/P1010 projects at Freescale Semiconductors. ( May

2010 )

. Designed and implemented an arithmetic unit based on Residue Number

system. The design was simulated using VHDL. (Jan '06 - May '07,BIT

Mesra)

AWARDS

. Engineering Award for paper on "Antenna Immune Power Grid design in

45SOI Technology" (Freescale, 2010).

. BRAVO award for outstanding performance and contributions to the

project Beagle at Freescale semiconductors (2008).

. Part of the design team at Freescale awarded Diamond Chip Award.(2008)

. Second prize in Paper Presentation Competition during technical meet

TECHNIEEK organized by IET(former IEE) student's chapter at BIT,

Mesra.(2004)

. Engineering Scholar- Ranked 3rd in the department of Electronics and

Communication Engineering amongst a batch strength of 87. (2007)

. Secretary of IEE student's chapter at BIT, Mesra. (2006-07)

. Gold medalist in Women's badminton category at the 10th Annual CRY

Cadence tournament.( 2009 and 2010)

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