Engineer Design
Resume:
Gary Olson
**** ******* *****, ****** *****, TX 75028-2674
*******@*****.***
Senior FPGA Engineer
Expertise in Field-Programmable Gate Array (FPGA) design and development. Complete knowledge of architecture definition, requirements development, algorithm development, and implementation of complex FPGA(s).
Technical ProficienciesVHDL, Verilog, System Verilog Language.Familiar with System Verilog and UVM. Mentor Graphics HDL Designer for FPGA architecture definition and project management.ModelSim/ALDEC Riviera Pro for simulation and verification of FPGA and board level designs.Synplify Pro, Precision design synthesis.Altera Quartus II, Xilinx ISE timing verification and Place and Route (PAR).Vendor specific IP development for optimized functional implementation.Technical documentation of requirements, design specifications, and requirements traceability.
Professional Experience
Overture, Richardson, TX 2009 – Oct2012
Senior FPGA Engineer II
Designed and implemented FPGA centric hardware solutions for a $70 million Carrier Ethernet Edge and Aggregation start-up.
Created PCIe Endpoint design to provide remote processor access to main fabric and daughter board memory mapped interfaces.Designed SLA performance counter module for multi-access carrier Ethernet platforms (4x1G and 6x10G). This module maintained 128K 64Bit counters.Created Nios embedded processor design to implement a Multilink PPP design.Designed and tested parts of a comprehensive service OAM suite.Integrated, tested, and verified HW/SW in lab using 10G test equipment and FPGA embedded logic analyzer.
Interphase, Plano, TX 2009 – 2009
Senior FPGA Engineer
Contract to design and implement processor centric FPGA solution for Quad OC-3/OC-12 Interworking Packet Processor to quad GigE carrier.
Implemented feature enhancements using Verilog in a Xilinx V4 FPGA design using the embedded PPC405. DDR2 processor and packet memory.Fixed third party DDR2 memory interface problems by using vendor specific IP development tools.Used Verilog to add per flow packet header sequence count for 14,000 flow interworking packet processor.Designed new IP embedded memory interfaces to free up limited resources so new features could be implemented.
Tellabs, Dallas, TX 1998 – 2009
(AFC, Marconi, Reltec)
Senior Design Engineer
Designed and implemented FPGA centric hardware solutions for a $350 million Access Division of a telecommunications company.
Created data aggregation FPGA design using VHDL on Linux based digital card.Produced physical layer (OSI Layer1) and data link layer (OSI Layer2) interfaces to switches, DSPs, and other FPGAs across high speed printed circuit boards (PCB) and backplanes.Designed multi-protocol frame processor in VHDL for FPGA that verified PVCs, performed VLAN translation, VLAN/MAC security filtering, and IP MAC access control list (ACL) management.Demonstrated ability to manage multiple clock domains using synchronizing registers, Dual Port Memories, FIFOs, and interlocked FSMs.Designed FSMs to control peripherals, process control messages, and manage processor memory mapped interfaces. Created FPGA embedded processor design (Altera NIOS) to configure and manage fiber to the premises (FTTP) R&D system. Initialization, ranging, and packet transfers controlled by FPGA FSM.Designed backplane packet transfer protocol using asymmetric single data rate (SDR) and double data rate (DDR) transfers. This design maximized the bandwidth of a legacy product allowing the deployment of a new product line into a deployed base. This extended the product life cycle instead of obsolescing the product. Supervised the implementation of customer feature modifications implemented in FPGA. Used system engineering, software engineering, and vendor engineers to specify a switch-to-DSP specific encapsulation algorithm Ethernet-over-PTM-over-EFM used for VDSL2 implementation.Supervised the co-development and integration of a VOIP/proprietary POTS interface that was used in FTTC/FTTN products. Developed schedules for FPGA documentation, implementation, test, PAR, timing closure, and integration.
Raytheon Optical Systems, Albuquerque, NM 1995 – 1998
Senior Engineer
Designed and implemented custom signal processing solutions for $2 million electro-optical Air Force research program.
Used customer specifications to create requirements documentation, design requirements, and verification test requirements.Developed signal processing algorithms using MATLAB for FPGA application.Developed digital boards using FPGAs, processors, discrete memories, DSPs, A/D and D/A devices.Routing of high speed signal traces to reduce cross-talk and reflections.PCB termination techniques for signal conditioning.Developed VME 6U and 9U digital boards for signal processing applications.
Hughes Aircraft Company, Fullerton, CA 1984 – 1995
Engineer II
Designed digital boards using processors, discrete memories, DSPs, and CPLDs for a VME based architecture. Large scale system development, test, and integration for U.S. Navy.
EducationBachelor of Science in Electrical Engineering (B.S.E.E.), California State Polytechnic University, CA
CredentialsInitialization and Monitoring System Patent on behalf of Tellabs US 6,795,538 B1 Sep. 21, 2004.Copper Based Interface System Patent on behalf of Tellabs US 6,775,299 B1 Aug. 10, 2004.Design and Development of a Wavefront Reconstructor, Co-authored 1997. The ICSPAT 1997 Conference Proceedings.
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